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MSMXVHF датащи(PDF) 4 Page - Mixed Signal Integration |
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MSMXVHF датащи(HTML) 4 Page - Mixed Signal Integration |
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4 / 7 page ![]() Filter Selection The filter type is selected using the two filter se- lect pins, TYPE and FSEL, FSEL is a CMOS level pin that selects lowpass or bandpass response (lowpass = 0, bandpass = 2). TYPE Is a tertiary control pin that selects the filter response. State 0 is VSS, state 1 is AGND and state 2 is VDD. TYPE Lowpass Bandpass 0 Butterworth Full Octave 1 Bessel Third Octave 2 Elliptic Sixth Octave Pin Description 1. TYPE Filter Response Select Pin. 2. FCLK Filter Clock Input 3. G Gain Select Pin 4. PWR Power Select Pin; CMOS level High= Regular Power; Low=Low Power 5. VDD Positive Power Supply,Typically +1.5 Volts for Split Supply, +3.0 Volts for Single Supply 6. PDown Power Down Pin, CMOS level, Hi = Power Down 7, VSS Negative Power Supply,Typically -1.5 Volts for Split Supply, 0 Volts for Single Supply 8. MCLK Mixer Clock: CMOS Levels 9. F0 Clock to Corner Select Pin 10. MO Mixer Output 11. AGND GND Pin, OV for Split Supplies +1.5 Volts Typical for Single Supply 12. FIN Filter Input 13. MIX2 Mixer Input 2 14. MIX1 Mixer Input 1 15. FSEL Filter Select 2 = Banpass; 0= Lowpass 16. FOUT Filter Output Gain and Frequency Selection The Gain select pin G is a tertiary control pin where state 0 is VSS, state 1 is AGND level and state 2 is VDD. G Gain 0 OdB 1 10dB 2 20dB The clock to corner select pin F0 is a CMOS level pin where HIGH is clock to corner of 12.5 to 1 (25 to 1 for Bessel) and LOW is clock to corner of 6.25 to 1 (12.5 to 1 for Bessel). The sample rate ratio is twice the clock to corner ratio (double sampling). Pin Configuration ©2011-2 2014 Mixeed Signal Inteegratioon 4 Weeb Sitee ““www.mix-ssig.coom”” 6/2014 High Frequency Mixxer and Selecttable VHF LP//BP Filtter Datta Sheett 1 2 3 4 5 6 7 14 13 12 11 10 9 8 16 15 TYPE MCLK FO FCLK G PWR VDD PD VSS MO AGND FIN MIX2 MIX1 FSEL FOUT |
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