Tone Dettecttor

Datta Sheett

PARAMETER

SYMBOL

CONDITIONS

MIN TYP

MAX

UNITS

DC Specifications

Operating Voltage

VDD

2.7

5.5

V

Supply Current

IDD

0.2

0.6

2.0

mA

Digital Outputs levels

0.5

VDD-0.5

VDC

Internal Voltage Reference

VREF

1.21 VDD.0.5

VDC

AC Specifications

Input Tone Voltage

10

50

1000

mVp-p

FSK Input Impedance

10

24

kohms

VCO Minimum Frequency

R = 100 kohms C = 22 uF

1

Hz

VCO Maximum Frequency

R = 10 kohms C= 470 pF

90

kHz

VCO Loop Gain

8

Radians/Sec/V

Phase Comparator Gain

2

V/Radians

Electrricaal Chaarraacterristics

(VDD = 5.0V, T = 25o C)

©2004-2

2014 Mixeed Signal Inteegratioon

2

Weeb Sitee ““www.mix-ssig.coom””

Prrinciples of Operraation

The VCO in the MSDET oscillates at twice the

detected frequency. The formula used for the tone

detection is:

fVCO = 1/(3.35.R.C)

Internal flip-flops generate the quadrature clock need-

ed for both FSK detection and coherent carrier

detect.

This is fed to two phase comparators.

The QOUT of the MSDET is filtered and tied to

VIN to close the loop and allow the phase error to

control the VCO frequency.

With all analog PLLs there is a tendency to lock to

third-harmonic of the desired tone.

By using exter-

nal filters and coupling capacitors, this characteristic

can be minimized. The application schematic of the

MSDET shows a low-value input coupling capacitor

applying received signals to the input gain stage.

This reduces sub-harmonic lock.

1

2

3

4

5

6

7

14

13

12

11

10

9

8

16

15

VREF

CVIN

QOUT

LOUT

NC4

NC5

NC6

VDD

R

IN

LPOUT

LPIN

DIN

DOUT

VSS

6/2014