SM320VC33 datasheet(39/54 Pages) TI

39 / 54 page

SM320VC33, SMJ320VC33

DIGITAL SIGNAL PROCESSOR

SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251-1443

reset timing (continued)

EXTCLK

RESET

(see Notes A and C)

IACK

D[31:0]

PAGEx, A[23:0]

STRB

Asynchronous

Reset Signals

(see Note B)

R/W

Ten H1 Clock Cycles

tsu(RESET-EXTCLKL)

td(EXTCLKH-H1H)

td(EXTCLKH-H1L)

td(EXTCLKH-H3L)

tsu(RESETH-H1L)

tdis(H1H-DZ)

td(EXTCLKH-H3H)

td(H3H-CONTROLH)

tdis(H3H-AZ)

td(H1H-RWH)

td(H1H-IACKH)

tdis(RESETL-ASYNCH)

NOTES: A. Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3.

B. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.

C. RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are met, the exact

sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.

D. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the

reset vector is fetched twice, with no software wait states.

E. The address and PAGE3-PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10-22 k

Ω pullup.

If not, undesirable spurious reads can occur when these outputs are not driven.

Figure 27. RESET Timing

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