NM1482KSLAXCL datasheet(4/121 Pages) NANYA

4 / 121 page

Version 1.6

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 2Gb LPDDR2

NM148(F)2KSLAXCL/NM1482NSLAXCL

NTC Proprietary

Level: Property

Features

MCP

 Separate SLC NAND and LPDDR2 RAM interfaces

 Lead-free (RoHS compliant) and Halogen-free Package : 162-ball FBGA 8.00 x 10.50 x 1.00 (mm)

 Operating temperature range: –25°C to +85°C

4Gb X8/X16 SLC NAND

 Voltage Supply(VCC/VCCQ): 1.70V ~ 1.95V

 Organization

- X8 Memory Cell Array: 4352 x 128K x 8

- X8 Register: 4352 x 8

- X8 Page Program: 4352 Bytes

- X8 Block Erase: (256K + 16K) Bytes

- X16 Memory Cell Array: 2176 x 128K x 16

- X16 Register: 2176 x 16

- X16 Page Program: 2176 Words

- X16 Block Erase: (128K + 8K) Words

 Modes

Read, Reset, Auto Page Program, Auto Block Erase,

Status Read, Page Copy, Multi Page Program,

Multi Block Erase, Multi Page Copy, Multi Page Read

 Mode control

- Serial input/output

- Command control

 Number of valid blocks

- Min 2008 blocks

- Max 2048 blocks

 Access time

- Cell array to register

: 25μs max

- Serial Read Cycle: 25ns min (CL=30pF)

 Program/Erase time

- Auto Page Program: 30

0μs/page typical

- Auto Block Erase: 3.5ms/block typical

 Operating current

- Read (25ns cycle): 30 mA max

- Program (avg.): 30 mA max

- Erase (avg.): 30 mA max

- Standby: 50

μA max

 8 bit ECC for each 512 Bytes is required.

2Gb X16/X32 LPDDR2

 Speed, Addressing and Retention Specification

Organization

128Mb x 16

64Mb x 32

Speed Grade

1066 / RL=8

Device Type

S4B

Number of Banks

Bank Address

BA0-BA2

Row

R0-R13

Column

C0-C9

C0-C8

tREFI (us)

3.9

 JEDEC LPDDR2 Compliant

- Low Power Consumption

- Double-data rate on DQs, DQS, DM and CA bus

- 4n Prefetch Architecture

 HSUL12 interface and Power Supply

- VDD1= 1.70 to 1.95V

- VDD2/VDDQ/VDDCA = 1.14 to 1.3V

 Signal Integrity

- Configurable DS for system compatibility

- ZQ calibration for the accuracy of output driver strength

over Process, Voltage and Temperature

 Training for Signals

’ Synchronization

- DQ Calibration offering specific DQ output patterns

 Data Integrity

- DRAM built-in Temperature Sensor for Temperature

Compensated Self Refresh (TCSR)

- Auto Refresh, Self Refresh and PASR Modes

 Power Saving Modes

- Deep Power Down Mode (DPD)

- Partial Array Self Refresh (PASR)

- Clock Stop capability during idle period

 Programmable Function

- Output Drive Impedance (34.3/40/48/60/80/120)

- Burst Lengths (4/8/16)

- Burst Type (Sequential/Interleaved)

- Read Latency (3/4/5/6/7/8),Write Latency (1/2/3/4)

- nWR (3/4/5/6/7/8)

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