CS5334 datasheet(12/20 Pages) CIRRUS

12 / 20 page

3. running the high pass filter with a fast settling

time constant,

4. freezing the dc offset register, and

5. reconnecting the internal ADC inputs to the

input pins.

This procedure takes 4,160 cycles of LRCK.

Unlike the system calibration procedure de-

scribed in the High Pass Filter section, a dc

calibration performed during start-up will only

eliminate offsets internal to the CS5334/5, and

should result in output codes which accurately

reflect the differential dc signal at the pins.

Power-Down

The CS5334 and CS5335 have a power-down

mode wherein typical consumption drops to 1.0

mW. This is initiated when a loss of clock is de-

tected (either LRCK or MCLK in Slave Mode or

MCLK in Master Mode), RST is enabled or

DIF0 / DIF1 are at a logic 1. The initialization

sequence will begin whenever valid clocks are

restored, RST is disabled and DIF0 / DIF1 are

restored. If the MCLK / LRCK frequency ratio

changes during power-down, the CS5334/5 will

adapt to these new operating conditions. How-

ever, only the RST method of power-down will

include the Master/Slave decision in the initiali-

zation sequence.

Grounding and Power Supply Decoupling

As with any high resolution converter, the

CS5334 and CS5335 require careful attention to

power supply and grounding arrangements to op-

timize

performance.

Figure

shows

the

recommended power arrangements with VA+

connected to a clean +5 volt supply. VD+ should

be derived from VA+ through a 2 ohm resistor.

VD+ should not be used to power additional

digital circuitry. All mode pins which require

VD+ should be connected to pin 6 of the

CS5334/5. All mode pins which require DGND

should be connected to pin 5 of the CS5334/5.

AGND and DGND, Pins 4 and 5, should be con-

nected together at the CS5334/5. DGND for the

CS5334/5 should not be confused with the

ground for the digital section of the system. The

CS5334/5 should be positioned over the analog

ground plane near the digital / analog ground

plane split. The analog and digital ground planes

must be connected elsewhere in the system. The

CS5334/5 evaluation board, CDB5334/5, demon-

strates this layout technique. This technique

minimizes digital noise and insures proper power

supply matching and sequencing. Decoupling ca-

pacitors should be located as near to the

CS5334/5 as possible.

CS5334 CS5335

DS237PP2

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