GPF32001A datasheet(4/21 Pages) GENERALPLUS

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GPF32001A

Proprietary & Confidential

Nov. 29, 2016

Version: 1.0

Advanced 16-Bit SoC with

’nSP® 2.0

1. GENERAL DESCRIPTION

The Generalplus GPF32001A is highly integrated system-on-a

chip

and

targets

cost-effective,

high

performance

micro-controller solution for electronic dictionary, education and

learning applications.

It embeds a

’nSP® 2.0 (16-bit CPU

developed by Sunplus) with 4KB I-cache, 32 channels sound

process

unit

(SPU),

SDRAM

controller,

ROM/SRAM/NOR

FLASH/NAND FLASH with ECC Memory controller, UART/IrDA

interface, four channel DMA controller, six-channel 16-bit timers,

SD/MMC

memory

interface,

USB

mini-host/device,

mono

STN-LCD

and

TFT-LCD

interface,

interrupt

controller,

SPI

master/slave controller, Key scan controller, programmable I/O

ports, 16-bit DAC for audio playback, 12-bit ADC, PLL, and

embedded 28K*16-bit SRAM.

By providing a complete set of common system peripherals, the

Generalplus GPF32001A chip minimizes overall system costs and

eliminates the need to configure additional components.

The

GPF32001A provides not only the high-speed performance and

low cost for a system, but it also integrates several powerful tools

into the development system, such as development system with C

language, assembly compiler, linker, source debugger functions

and project management tools.

2. BLOCK DIAGRAM

SDRAM

ROM/RAM/

NOR FLASH

NAND FLASH

Controller

’nSP™ 2.0

With ICE

Key SCAN

USB Transceiver

RTC

PLL

16-bits DACx2

5ch 12-bits ADC

Regulator

System Control

DAC/ADC Control

SRAM 28K*16

4-ch DMA

USB

mini-host/device

Controller

UART/IrDA

SPI Master/Slave

Serial IO

STN/TFT-LCD

SD/MMC Controllerx2

6 Timers

2K*16 I-Cache

32-ch SPU

Video-In

CMOS Sensor

3. FEATURES



’nSP® 2.0 16-bit CPU with frequency up to 96MHz.

 4K bytes I-cache.

 28k*16-bit SRAM for programming or LCD frame buffers.

 Sound Process Unit (SPU)

 32 hardware PCM/ADPCM channels.

 Built-in sound compressor.

 MP3 decoder.

 Video-in/CMOS sensor interface supports CCIR601/CCIR656

standard.

 96 MHz SDRAM with maximum size 64M bytes for single chip

selection.

 Static memory controller. (ROM/ SRAM/ NOR FLASH/ Page

Memory/ NAND FLASH with ECC)

 Four-channel DMA controller.

 Mono and 16 gray STN-LCD controller.

 TFT-LCD controller which can be UPS051 (serial RGB),

UPS052 (serial RGB dummy), parallel RGB, i80 (8-bit/16-bit

system bus) I/F type, and CCIR601/CCIR656.

 Twenty-eight sources Interrupt Controller.

 Universal Serial Bus (USB) 2.0 full speed compliant device and

USB mini-host with built-in transceiver.

 Watchdog timer.

 Real-time clock.

 Six 16-bit timers.

 Two sets SD/MMC memory interface.

 SPI master/slave interface.

 UART (asynchronous serial I/O) or IrDA interface.

 74 Programmable general I/O ports (GPIO) with pull-high/low

control.

 64/88 keys scan controller with velocity detection.

 Power manager.

 Built-in 3.0V to 1.8V Regulator.

 Low voltage reset.

 96MHz, 27MHz and 12MHz PLL.

 16-bit stereo DAC (2ch) for audio playback.

 12-bit ADC with 4 line-in and 1 microphone input.

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