GPCE040A datasheet(7/26 Pages) GENERALPLUS

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GPCE040A

Proprietary & Confidential

Oct 01, 2013

Version: 1.4

6.FUNCTIONAL DESCRIPTIONS

6.1. CPU

The GPCE040A is equipped with a 16-bit

μ’nSP™, the newest

16-bit microprocessor by Sunplus and pronounced as micro-n-SP.

Eight registers are involved in

μ’nSP™: R1 - R4 (General-purpose

registers), PC (Program Counter), SP (Stack Pointer), Base

Pointer (BP) and SR (Segment Register).

The interrupts include

three FIQs (Fast Interrupt Request) and eight IRQs (Interrupt

Request), plus one software-interrupt, BREAK.

Moreover, a high performance hardware multiplier with the

capability of FIR filter is also built in to reduce the software

multiplication loading.

6.2. Memory

6.2.1. SRAM

The amount of SRAM is 2K-word (including Stack), ranged from

$0000 through $07FF with access speed of two CPU clock cycles.

Fosc/n

n:1,2,4,8,16,32,64

of P_System C lock(W )($7013H )

C PU clock frequency selection

CPU Clock

32768H z X'tal

b7,b6,b5 of P_System C lock(W )($7013H )

System clock frequency selection

(D efault : Fosc/8)

Phase Lock Loop

(PLL)

System C lock

generator

PLL O U T

FO SC

24.576M H z(default)

20.48M H z

32.768M H z

40.96M H z

49.152M H z

6.2.2. ROM

The GPCE040A provides a 24K-word fast-speed ROM with

access speed of two CPU clock cycles.

6.3. PLL, Clock, Power Mode

6.3.1. PLL (Phase Lock Loop)

The purpose of PLL is to provide a base frequency (32768Hz) and

to pump the frequency from 20.48MHz to 49.152MHz for system

clock (FOSC).

The default PLL frequency is 24.576MHz.

6.3.1.1. System clock

Basically, the system clock is provided by PLL and programmed

by the Port_SystemClock (W) to determine the frequency of clock

for system.

The default system clock FOSC = 24.576MHz and

CPU clock is Fosc/8 if not specified.

The initial CPU clock is

Fosc/8 after system wakes up and to be adjusted to desired CPU

clock by programming the Port_SystemClock (W).

6.3.1.2. 32768Hz RTC

The Real Time Clock (RTC) is normally used in watch, clock or

other time related products.

A 2Hz-RTC (1/2 second) function is

loaded in GPCE040A.

The RTC counts the timing as well as to

wake CPU up whenever RTC occurs.

Since the RTC is

generated in every 0.5 seconds, time can be traced by the

numbers of RTC occurrence.

In addition, GPCE040A supports

32768Hz oscillator in normal mode and auto-power-saving mode.

In normal mode, 32768Hz OSC always runs at the highest power

consumption.

In auto-power-saving mode, however, it runs in

normal mode for the first 7.5 seconds and changes back to

power-saving mode automatically to save powers.

6.4. Standby Mode

The GPCE040A also offers a standby mode for low power

application needs.

To enter standby mode, the desired key

wakeup port(IOA[7:0]) must be configured to input first.

And read

the Port_IOA_Latch(R) to latch the IOA state before entering the

standby mode.

Also remember to enable the corresponding

interrupt source(s) for wakeup.

After that, stop the CPU clock by

writing the STOP CLOCK Register (b0~b2 of Port_SystemClock

(W)) to enter standby mode.

In such mode, SRAM and I/Os

remain in the previous states till CPU being awoken.

The

wakeup sources in GPCE040A include Port IOA7 - 0 and IRQ1 -

IRQ6.

After GPCE040A is awoken, the CPU will continue to

execute the program.

Programmer can also enable or disable

the 32768Hz OSC when CPU is in standby mode.

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