High Speed CMOS Logic – 54HC139

Rev 1.0

16/04/18

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

 

FULL RANGE

4

UNITS

2.0V

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1.9

1.9

1.9

4.5V

4.4

4.4

4.4

6.0V

5.9

5.9

5.9

4.5V

3.98

3.84

3.70

Minimum High-Level

Output Voltage

V

6.0V

5.48

5.34

5.20

2.0V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

0.1

0.1

0.1

4.5V

0.26

0.33

0.40

Maximum Low-Level

Output Voltage

6.0V

0.26

0.33

0.40

V

Maximum Input

Leakage Current

6.0V

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Current

6.0V

4

40

160

µA

LIMITS

PARAMETER

6. Not production tested in die form, characterized by chip design and tested in package.

SYMBOL

CONDITIONS

UNITS

FULL RANGE

4

25°C

85°C

2.0V

115

145

175

4.5V

23

29

35

Maximum

Propagation Delay,

ns

Select to Output Y

(Figure 1, 3)

6.0V

20

25

30

2.0V

115

145

175

4.5V

23

29

35

Maximum

Propagation Delay,

ns

Input A to Output Y

(Figure 2,3)

6.0V

20

25

30

2.0V

75

95

110

4.5V

15

19

22

Maximum Output

Transition Time,

ns

Any Output

(Figure 1,3)

6.0V

13

16

19

Maximum Input

Capacitance

-

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance

(Per Decoder)

7

-

55

pF

 

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