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High Speed CMOS Logic – 74HC112

Rev 1.0

24/11/17

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

165

205

205

4.5V

33

41

41

Maximum Propagation

Delay,

Set to Q or Q

(Figure 2,4)

6.0V

28

35

35

ns

2.0V

75

95

95

4.5V

15

19

19

Maximum Output

Transition time,

Any output

(Figure 1,4)

6.0V

13

16

16

ns

Maximum Input

Capacitance

-

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance

6

(Per Flip-Flop)

-

-

35

pF

5. Not production tested in die form, characterized by chip design and tested in package.

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

100

125

125

4.5V

20

25

25

Maximum Setup Time,

J or K to Clock

(Figure 3)

6.0V

17

21

21

ns

2.0V

3

3

3

4.5V

3

3

3

Minimum Hold Time,

Clock to J or K

(Figure 3)

6.0V

3

3

3

ns

2.0V

100

125

125

4.5V

20

25

25

Minimum Recovery

Time, Set or Reset

Inactive to Clock

(Figure 2)

6.0V

17

21

21

ns

2.0V

80

100

100

4.5V

16

20

20

Minimum Pulse Width,

Clock

(Figure 1)

6.0V

14

17

17

ns

2.0V

80

100

100

4.5V

16

20

20

Minimum Pulse Width,

Set or Reset

(Figure 2)

6.0V

14

17

17

ns

2.0V

1000

1000

1000

4.5V

500

500

500

Maximum Input Rise

and Fall times

(Figure 1)

6.0V

400

400

400

ns