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¡ Semiconductor

MSM82C53-2RS/GS/JS

Reading of Counter Values

All MSM82C53-2 counting is down-counting, the counting being in steps of 2 in mode 3.

Counter values can be read during counting by (1) direct reading, and (2) counter latching

(“read on the fly”).

• Direct reading

Counter values can be read by direct reading operations.

Since the counter value read according to the timing of the RD and CLK signals is not

guaranteed, it is necessary to stop the counting by a gate input signal, or to interrupt the clock

input temporarily by an external circuit to ensure that the counter value is correctly read.

• Counter latching

In this method, the counter value is latched by writing counter latch command, thereby

enabling a stable value to be read without effecting the counting in any way at all. An example

of a counter latching program is given below.

Counter latching executed for counter #1 (Read/Load 2-byte setting)

0 1 0 0 ¥ ¥ ¥ ¥

MVI A

Dentotes counter latching

OUT n3

Write in control word address (n3)

IN n1

Reading of the LSB of the counter

value latched from counter #1

n1: Counter #1 address

MOV B, A

IN n1

MOV C, A

Reading of MSB from counter #1

The counter value at this point is latched.

MSM82C53-2

Use counter #1 and counter #2

Counter #1: mode 0, upper order 16-bit counter

value

Counter #2: mode 2, lower order 16-bit counter

value

Example of Practical Application

• MSM82C53-2 used as a 32-bit counter.