CDC913

PC MOTHERBOARD CLOCK GENERATOR

WITH DUAL 1-TO-4 BUFFERS AND 3-STATE OUTPUTS

SCAS502C – APRIL 1995 – REVISED MAY 1996

2

POST OFFICE BOX 655303

Function Tables

SEL0

SEL1

X1

CPUCLK

PCICLK

REFCLK

L

L

14.318 MHz

50 MHz

33 MHz

14.318 MHz

H

L

14.318 MHz

60 MHz

33 MHz

14.318 MHz

L

H

14.318 MHz

66 MHz

33 MHz

14.318 MHz

H

H

TCLK†

TCLK†

TCLK†

TCLK†

† Test clock (TCLK) is driven over X1 when the CDC913 is in the TEST mode; i.e.,

SEL1 = SEL0 = H.

OE

1A

2A

1Yn

2Yn

H

X

X

Hi-Z

Hi-Z

L

L

L

L

L

L

L

H

L

H

L

H

L

H

L

L

H

H

H

H