2

AT40KAL Series FPGA

2818ES–FPGA–1/04

Note:

1. Packages with FCK will have 8 less registers.

Description

The AT40KAL is a family of fully PCI-compliant, SRAM-based FPGAs with distributed

10 ns programmable synchronous/asynchronous, dual-port/single-port SRAM, 8 global

clocks, Cache Logic ability (partially or fully reconfigurable without loss of data), auto-

matic component generators, and range in size from 5,000 to 50,000 usable gates. I/O

counts range from 128 to 384 in industry standard packages ranging from 84-pin PLCC

to 352-ball Square BGA, and support 3.3V designs.

The AT40KAL is designed to quickly implement high-performance, large gate count

designs through the use of synthesis and schematic-based tools used on a PC or Sun

platform. Atmel’s design tools provide seamless integration with industry standard tools

such as Synplicity, ModelSim, Exemplar and Viewlogic. See the “IDS Datasheet” avail-

able on the Atmel web site (http://www.atmel.com/atmel/acrobat/doc1421.pdf) for a list

of other supported tools.

The AT40KAL can be used as a coprocessor for high-speed (DSP/processor-based)

designs by implementing a variety of computation intensive, arithmetic functions. These

include adaptive finite impulse response (FIR) filters, fast Fourier transforms (FFT), con-

volvers, interpolators and discrete-cosine transforms (DCT) that are required for video

compression and decompression, encryption, convolution and other multimedia

applications.

Fast, Flexible and

Efficient SRAM

The AT40KAL FPGA offers a patented distributed 10 ns SRAM capability where the

RAM can be used without losing logic resources. Multiple independent, synchronous or

asynchronous, dual-port or single-port RAM functions (FIFO, scratch pad, etc.) can be

created using Atmel’s macro generator tool.

Fast, Efficient Array and

Vector Multipliers

The AT40KAL’s patented 8-sided core cell with direct horizontal, vertical and diagonal

cell-to-cell connections implements ultra fast array multipliers without using any busing

resources. The AT40KAL’s Cache Logic capability enables a large number of design

coefficients and variables to be implemented in a very small amount of silicon, enabling

vast improvement in system speed at much lower cost than conventional FPGAs.

Table 1. AT40KAL Family

(1)

Device

AT40K05AL

AT40K10AL

AT40K20AL

AT40K40AL

Usable Gates

5K - 10K

10K - 20K

20K - 30K

40K - 50K

Rows x Columns

16 x 16

24 x 24

32 x 32

48 x 48

Cells

256

576

1,024

2,304

Registers

496

(1)

954

(1)

1,520

(1)

3,048

(1)

RAM Bits

2,048

4,608

8,192

18,432

I/O (Maximum)

128

192

256

384