W256
Document #: 38-07256 Rev. *C
Page 5 of 9
Switching Characteristics[4]
Parameter
Name
Test Conditions
Min.
Typ.
Max.
Unit
–
Operating Frequency
66
180
MHz
–
Duty Cycle[4,5] = t2 ÷ t1
Measured at 1.4V for 3.3V outputs
Measured at VDD/2 for 2.5V outputs.
INDC
–5%
INDC +5%
%
t3
SDRAM Rising Edge Rate[4]
Measured between 0.4V and 2.4V
1.0
2.50
V/ns
t4
SDRAM Falling Edge Rate[4]
Measured between 2.4V and 0.4V
1.0
2.50
V/ns
t3d
DDR Rising Edge Rate[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
0.5
1.50
V/ns
t4d
DDR Falling Edge Rate[4]
Measured between 20% to 80% of
output (Refer to Figure 1)
0.5
1.50
V/ns
t5
Output to Output Skew[4]
All outputs equally loaded
100
ps
t6
Output t4o Output Skew for
SDRAM[2]
All outputs equally loaded
150
ps
t7
SDRAM Buffer HH Prop. Delay[4] Input edge greater than 1 V/ns
5
10
ns
t8
SDRAM Buffer LLProp. Delay[4]
Input edge greater than 1 V/ns
5
10
ns
Switching Waveforms
Notes:
4. All parameters specified with loaded outputs.
5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.
Duty Cycle Timing
t1
t2
All Outputs Rise/Fall Time
OUTPUT
t3
3.3V
0V
0.4V
2.4V
2.4V
0.4V
t4
Output-Output Skew
t5
OUTPUT
OUTPUT
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