RFM75 V2.0

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Page 21 of 27

7.2

Register Bank 1

Address

(Hex)

Mnemonic

Bit

Reset

Value

Type

Description

00

31:0

0

W

Must write with 0x404B01E2

01

31:0

0

W

Must write with 0xC04B0000

02

31:0

0

W

Must write with 0xD0FC8C02

03

31:0

0x

03001200

W

Must write with 0x99003921

04

31:0

0

W

Must write with

1Msps：0xF996821B

2Msps: 0xF99682DB

250ksps：0xF9968ADB

For single carrier mode:0xF9968221

05

31:0

0

W

Must write with

1Msps：0x24060FA6(Disable RSSI)

2Msps：0x 24060FB6(Disable RSSI)

250ksps:0x24060FB6(Disable RSSI)

RSSI_EN

18

0

W

RSSI measurement:

0:Enable

1:Disable

06

31:0

0

W

Reserved

07

31:0

0

W

Reserved

RBANK

7

R

Register bank selection states. Switch

register bank is done by SPI command

“ACTIVATE” followed by 0x53

0: Register bank 0

1: Register bank 1

08

Chip ID

31:0

0

R

BEKEN Chip ID:

0x00000063(RFM75)

09

0

Reserved

0A

0

Reserved

0B

0

Reserved

0C

31:0

0

W

Please initialize with 0x05731200

For 120us mode:0x00731200

26:24

101

PLL Settling time:

101:130us

000:120us

9

1

Compatible mode:

0:Static compatible

1:Dynamic compatible

0D

NEW_FEATURE

31:0

0

Please initialize with 0x0080B436

0E

RAMP

87:0

NA

W

Ramp curve

Please write with

0x FFFFFEF7CF208104082041

Note: Don’t write reserved registers and no definition registers in register bank 1

Table 5 Register Bank 1