PIC12F635ESLASHMFQTP datasheet(69/196 Pages) MICROCHIP

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Preliminary

DS41232B-page 67

PIC12F635/PIC16F636/639

7.4

Comparator Outputs

The comparator outputs are read through the

CMCON0 register. These bits are read-only. The

comparator outputs may also be directly output to the

RA2 and RC4 I/O pins. When enabled, multiplexers in

the output path of the RA2 and RC4 pins will switch

and the output of each pin will be the unsynchronized

output of the comparator. The uncertainty of each of

the comparators is related to the input offset voltage

and the response time given in the specifications.

Figure 7-5 and Figure 7-6 show the output block

diagrams for Comparator 1 and 2.

The TRIS bits will still function as an output enable/

disable for the RA2 and RC4 pins while in this mode.

The polarity of the comparator outputs can be changed

using the C1INV and C2INV bits (CMCON0<5:4>).

Timer1 gate source can be configured to use the T1G

pin or Comparator 2 output as selected by the T1GSS bit

(CMCON1<1>). This feature can be used to time the

duration or interval of analog events. The output of

Comparator 2 can also be synchronized with Timer1 by

setting the C2SYNC bit (CMCON1<0>). When enabled,

the output of Comparator 2 is latched on the falling edge

of the Timer1 clock source. If a prescaler is used with

Timer1, Comparator 2 is latched after the prescaler. To

prevent a race condition, the Comparator 2 output is

latched on the falling edge of the Timer1 clock source

and Timer1 increments on the rising edge of its clock

source. See Figure 7-6, Comparator C2 Output Block

Diagram and Figure 5-1, Timer1 on the PIC12F635/

PIC16F636/639 Block Diagram for more information.

It is recommended to synchronize Comparator 2 with

Timer1 by setting the C2SYNC bit when Comparator 2

is used as the Timer1 gate source. This ensures Timer1

does not miss an increment if Comparator 2 changes

during an increment.

7.5

Comparator Interrupts

The comparator interrupt flags are set whenever there

is a change in the output value of its respective

comparator. Software will need to maintain information

about the status of the output bits, as read from

CMCON0<7:6>, to determine the actual change that

has occurred. The CxIF bits (PIR1<4:3>) are the

Comparator Interrupt Flags. These bits must be reset in

software by clearing them to ‘0’. Since it is also possible

to write a ‘1’ to this register, a simulated interrupt may

be initiated.

The

CxIE

bits

(PIE1<4:3>)

and

the

PEIE

bit

(INTCON<6>) must be set to enable the interrupts. In

addition, the GIE bit must also be set. If any of these

bits are cleared, the interrupt is not enabled, though the

CxIF bits will still be set if an interrupt condition occurs.

The user, in the Interrupt Service Routine, can clear the

interrupt in the following manner:

Any read or write of CMCON0. This will end the

mismatch condition.

Clear flag bits CxIF.

A mismatch condition will continue to set flag bits CxIF.

Reading CMCON0 will end the mismatch condition and

allow flag bits CxIF to be cleared.

Note:

If a change in the CMCON0 register

(CxOUT) should occur when a read

operation is being executed (start of the

Q2 cycle), then the CxIF (PIR1<4:3>)

interrupt flags may not get set.

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