PIC12F635ESLASHST datasheet(95/196 Pages) MICROCHIP

95 / 196 page

Preliminary

DS41232B-page 93

PIC12F635/PIC16F636/639

11.29 Demodulator

The demodulator recovers the modulation data from

the received signal, containing carrier plus data, by

appropriate envelope detection. The demodulator has

a fast rise (charge) time (TDR) and a fall time (TDF)

appropriate to an envelope of input signal (see

Section 15.0 “Electrical Specifications” for TDR

and TDF specifications). The demodulator contains

the full-wave rectifier, low-pass filter, peak detector

and data slicer.

FIGURE 11-9:

DEMODULATOR CHARGE AND DISCHARGE

11.30 Power-On Reset

This circuit remains in a Reset state until a sufficient

supply voltage is applied to the AFE. The Reset

releases when the supply is sufficient for correct AFE

operation, nominally VPOR of AFE.

The Configuration registers are all cleared on a Power-

on Reset. As the Configuration registers are protected

by odd row and column parity, the ALERT pin will be

pulled down – indicating to the microcontroller section

that the AFE configuration memory is cleared and

requires loading.

11.31 LFDATA Output Selection

The LFDATA output can be configured to pass the

Demodulator output, Received Signal Strength Indicator

(RSSI) output, or Carrier Clock. See Configuration

11.31.1

DEMODULATOR OUTPUT

The demodulator output is the default configuration of

the output selection. This is the output of an envelope

detection circuit. See Figure 11-9 for the demodulator

output.

For a clean data output or to save operating power, the

input channels can be individually enabled or disabled. If

more than one channel is enabled, the output is the sum

of each output of all enabled channels. There will be no

valid output if all three channels are disabled. When the

demodulated output is selected, the output is available in

two different conditions depending on how the options of

Configuration Register 0 (Register 11-1) are set: Output

Enable Filter is disabled or enabled.

Related Configuration register bits:

• Configuration Register 1 (Register 11-2),

DATOUT <8:7>:

-bit 8 bit 7

: Demodulator Output

: Carrier Clock Output

: RSSI Output

• Configuration Register 0 (Register 11-1): all bits

Full-wave Rectifier output

Signal into LC input pins

Data Slicer output

TDR

TDF

(demodulator output)

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