IRMCF188

4

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© 2014 International Rectifier

March 10, 2017

List of Figures

Figure 1. Typical Application Block Diagram Using IRMCF188 .................................................................................5

Figure 2. Pinout of IRMCF188 ....................................................................................................................................6

Figure 3. IRMCF188 Block Diagram...........................................................................................................................7

Figure 4. IRMCF188 Leg Shunt Connection Diagram................................................................................................9

Figure 5. IRMCF188 Single Shunt Connection Diagram......................................................................................... 10

Figure 6. Crystal circuit example ............................................................................................................................. 18

Figure 7. Voltage droop and S/H hold time ............................................................................................................. 19

Figure 8 Op amp output capacitor ........................................................................................................................... 20

Figure 9. SYNC timing ............................................................................................................................................. 21

Figure 10. Gatekill timing ......................................................................................................................................... 22

Figure 11. ITRIP timing............................................................................................................................................ 22

Figure 12. Interrupt timing ....................................................................................................................................... 23

Figure 13. I

2C Timing............................................................................................................................................... 24

Figure 14. SPI write timing ...................................................................................................................................... 25

Figure 15. SPI read timing ....................................................................................................................................... 26

Figure 16. UART timing ........................................................................................................................................... 27

Figure 17. CAPTURE timing.................................................................................................................................... 28

Figure 18. JTAG timing............................................................................................................................................ 29

Figure 19. PWMUL/PWMUH/PWMVL/PWMVH/PWMWL/PWMWH output............................................................ 30

Figure 20. All digital I/O except motor PWM output ................................................................................................ 30

Figure 21. RESET, GATEKILL I/O .......................................................................................................................... 31

Figure 22. Analog input ........................................................................................................................................... 31

Figure 23. ADCL pin input structure ........................................................................................................................ 31

Figure 24 Analog operational amplifier output and AREF I/O structure ................................................................. 32

Figure 25. VSS,AVSS pin I/O structure ................................................................................................................... 32

Figure 26. VDD1,VDDCAP pin I/O structure ........................................................................................................... 32

Figure 27. XTAL0/XTAL1 pins structure.................................................................................................................. 33