EM8569 datasheet(10/12 Pages) EXCELLIANCE

10 / 12 page

2013/02/04

Rev.A.6

EM8569

Fig. 15

Soft Start

The EM8569 has an internal soft-start circuit that

increases cycle-by-cycle current limit comparator

inverting input voltage slowly after it starts. The

typical soft-start time is 3.5mS. The pulse width to

the power MOSFET is progressively increased to

establish

the correct

working conditions for

transformers, rectifier diodes and capacitors. The

voltage on the output capacitors is progressively

increased

with

the

intention

smoothly

establishing the required output voltage. It also

helps prevent transformer saturation and reduces

the stress on the secondary diode during startup.

Slope Compensation

In the conventional application, the problem of the

stability is a critical issue for current mode

controlling, when it operates in high than 50% of

the duty cycle. The EM8569 built in saw-tooth

slope compensation. So it requires no extra

component.

Brown-In/Out Function

The EM8569 has a built-in internal brown-in/out

protection comparator monitoring voltage of BNO

pin. Fig. 16 shows a resistive divider with low-pass

filtering for line-voltage detection on the BNO pin.

Fig. 16

If the BNO pin voltage is lower than 2.3V, the PWM

gate is disabled to protect the system from over

current. If the BNO pin increases above 2.8V, the

EM8569 starts up.

Deep Burst Mode Operation

At no load or light load condition, majority of the

power dissipation in switching power supply is

form switching loss on the power MOSFET, the

core loss of the transformer and the loss on the

snubber. The magnitude of power loss is in

proportion to the number of switching events

within a fixed period of time. Reducing switching

events leads reduction on the power loss and

conserves the energy.

The EM8569 adjusts the switching mode according

to the load condition, the COMP pin voltage drops

below Deep Burst mode in-threshold level (typical

1.3V). Device enters Deep Burst Mode Control. The

Gate drive output remains at off state to minimize

the switching loss and reduces the standby power

consumption. And when the COMP pin voltage

exceed the burst mode on threshold level (typical

1.4V). The Gate drive output starts active. The

COMP pin voltage immediately increases if there is

a high load. When the COMP pin voltage exceed

the Deep Burst mode out-threshold level (typical

1.5V), the device goes to normal mode. During the

Deep Burst mode, the CS level is controlled to 0.3V.

Fig. 17 shows the signals of Deep Burst mode.

GND

VCC

CVCC

HV curre nt source

HV MOS

EM8569

400 nS LEB

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