ALC885-GR datasheet(8/98 Pages) REALTEK

8 / 98 page

ALC885 Series

Datasheet

7.1+2 Channel High-Performance HDA Codec

With Content Protection

viii

Rev. 1.1

Table 90. Link Reset and Initialization Timing ........................................................................................79

Table 91. Link Timing Parameters at the Codec.......................................................................................80

Table 92. S/PDIF Output and Input Timing..............................................................................................81

Table 93. Analog Performance .................................................................................................................82

Table 94. Standby Mode ...........................................................................................................................86

Table 95. Volume Code Corresponding to DC Level at Pin 33................................................................87

Table 96. Ordering Information ................................................................................................................90

List of Figures

Figure 1.

Block Diagram ..........................................................................................................................4

Figure 2.

Analog Input/Output Unit .........................................................................................................5

Figure 3.

Pin Assignments ........................................................................................................................6

Figure 4.

HDA Link Protocol ...................................................................................................................9

Figure 5.

Bit Timing ...............................................................................................................................10

Figure 6.

Signaling Topology .................................................................................................................11

Figure 7.

SDO Outbound Frame.............................................................................................................12

Figure 8.

SDO Stream Tag is Indicated in SYNC ..................................................................................12

Figure 9.

Striped Stream on Multiple SDOs...........................................................................................13

Figure 10. SDI Inbound Stream................................................................................................................14

Figure 11. SDI Stream Tag and Data ........................................................................................................14

Figure 12. Codec Transmits Data Over Multiple SDIs.............................................................................15

Figure 13. Link Reset Timing...................................................................................................................19

Figure 14. Codec Initialization Sequence.................................................................................................20

Figure 15. Link Reset and Initialization Timing.......................................................................................79

Figure 16. Link Signals Timing ................................................................................................................80

Figure 17. Output and Input Timing .........................................................................................................81

Figure 18. Filter Connection.....................................................................................................................83

Figure 19. Front Panel Header Connection ..............................................................................................84

Figure 20. Jack Connection on Rear Panel...............................................................................................85

Figure 21. S/PDIF Input/Output Connection............................................................................................85

Figure 22. GPI Volume Control Implementation......................................................................................86

Figure 23. Volume Control by External Variable Resistor .......................................................................87

Figure 24. Digital Microphone Implementation-1....................................................................................88

Figure 25. Digital Microphone Implementation-2....................................................................................88

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