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FS9721_LP3-PCE датащи(PDF) 20 Page - Fortune Semiconductor Corp. |
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FS9721_LP3-PCE датащи(HTML) 20 Page - Fortune Semiconductor Corp. |
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20 / 39 page ![]() FS9721_LP3 Rev. 2.1 20/39 2*VDD 3.9V 1.2V 0.4V 1.5V 1.5V VGG VDDA REFO REFI VDD AGND VSS FS9721_LP3 RLCD 3V Diagram 9 Relative Voltage for Each Point VB is the IC internal bias current input. The increase of R4 will decrease IC internal current consumption, but insufficient bias current will influence AC measurement input range. AGND is the analog ground connection. Its potential is equal to the middle point of battery voltage. The potential of the point is generated by IC internal voltage that cannot connect to the middle point of battery. C4 and C5 are the bypass capacitances in one hand, and in the other hand to make AGND be regulated to VDD and VSS. C2 is power pump capacitance. IC makes VDD go through C2 to charge/discharge so as to raise VGG up to approximate double. VDDA is the output voltage after regulating VGG in the IC that is about 3.9V relative to VSS. REFO is the IC internal bandgap power that is about 1.2V relative to AGND, and has the stability of 100ppm/ . ℃ 15.3 Power Supply Circuit According to different application of users, the supply methods are different. In some measurements, all operating amplifier, Hale components and so on sensors require larger voltage so that it is difficult to supply by 3V. If so, the following supply methods are recommended: 10uF 10uF 3V VDD AGND VSS FS9721_LP3 Diagram 10 3V Power Supply |
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