394

PS8137A

03/15/99

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PI6C671F

Clock Generator for Pentium Modules

Power Management Functions

interface. All clocks stop in the LOW state. CPU, SDRAM, and PCI

clocks wait for one rising edge of PCICLK_F followed by a falling

#

P

O

T

S

_

U

P

C#

P

O

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_

I

C

P#

N

W

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R

W

P

,

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L

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A

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r

e

h

t

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k

c

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&

l

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r

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0

W

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LW

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LW

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Lf

f

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00

1

W

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LW

O

Lg

n

i

n

n

u

Rg

n

i

n

n

u

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01

1

W

O

Lz

H

M

0

3

/

3

3g

n

i

n

n

u

Rg

n

i

n

n

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R

10

1

z

H

M

0

6

/

6

6W

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Lg

n

i

n

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u

Rg

n

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n

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R

11

1

z

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M

0

6

/

6

6z

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M

0

3

/

3

3g

n

i

n

n

u

Rg

n

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n

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u

R

clock output and test mode enable.

The PI6C671F is a slave receiver device. It can not be read back.

Sub addressing is not supported. All preceding bytes must be sent

in order to change one of the control bytes.

Every bite put on the SDATA line must be 8-bits long (MSB first),

followed by an acknowledge bit generated by the receiving

device.

During normal data transfers SDATA changes only when SDCLK

is LOW. Exceptions: A HIGH to LOW transition on SDATA while

SDCLK is HIGH indicates a “start” condition. A LOW to HIGH

transition on SDATA while SDCLK is HIGH is a “stop” condition

and indicates the end of a data transfer cycle.

Each data transfer is initiated with a start condition and ended with

a stop condition. The first byte after a start condition is always a

7-bit address byte followed by a read/write bit. (HIGH = read from

addressed device, LOW= write to addressed device). If the device’s

own address is detected, PI6C671F generates an acknowledge by

pulling SDATA line LOW during ninth clock pulse, then accepts the

following data bytes until another start or stop condition is detected.

Following acknowledgement of the address byte (D2), two more

bytes must be sent:

1. “Command Code” byte, and

2. “Byte Count” byte.

Although the data bits on these two bytes are “don’t care,” they

must be sent and acknowledged.

Preset control register contents are retained.

I

Byte 0: Functional and Frequency Select

Clock Register (1 = enable, 0 = disable)

t

i

B.

o

N

n

i

Pp

u

r

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70

)

d

e

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r

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s

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(

60

)

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g

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n

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,

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(

50

)

e

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,

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(

40

)

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t

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n

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,

d

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s

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(

33

21

)

t

c

e

l

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S

q

e

r

F

(

z

H

M

4

2

/

8

4

z

H

M

4

2

=

0

,

z

H

M

8

4

=

1

22

21

)

t

c

e

l

e

S

q

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r

F

(

z

H

M

4

2

/

8

4

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H

M

4

2

=

0

,

z

H

M

8

4

=

1

1

0

0

0

0

t

i

B

1

t

i

B

e

t

a

t

S

-

i

r

T

:

1

1

m

u

r

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p

S

d

a

e

r

p

S

:

0

1

e

d

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t

s

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T

:

1

0

n

o

i

t

a

r

e

p

O

l

a

m

r

o

N

:

0

0

edge of the clock of interest before settling in the LOW state. To

reduce power consumption the PI6C671F clocks may be disabled in

accordance with the following table.