29 / 64 page
Ultra37000 CPLD Family
Document #: 38-03007 Rev. *D
Page 29 of 64
CY37128V
CY37192V
Typical 3.3V Power Consumption (continued)
0
10
20
30
40
50
60
70
80
0
2 0
4 0
6 0
8 0
100
1 2 0
140
Fr eque ncy (M H z )
Low P o w e r
H ig h S p eed
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
0
20
40
60
80
100
120
0
2 0
4 0
6 0
8 0
1 00
120
Fr eque ncy ( M H z )
Lo w P o w e r
Hig h S p e e d
The typical pattern is a 16-bit up counter, per logic block, with outputs disabled.
VCC = 3.3V, TA = Room Temperature
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