AT2008
8 Channels ADPCM Processor
Page 2 of 19
©2001 Atelic Systems, Inc.
PIN Description
PIN
SYMBOL
TYPE
DESCRIPTION
16
XIN
I
X Channel Data In. Sampled on the falling edge of CLKP during
selected time slots with MSB first.
20
XOUT
O
X Channel Data Out. Updated on the rising edge of CLKP during
selected time slots with MSB first.
27
YIN
I
Y Channel Data In. Sampled on the falling edge of CLKA during
selected time slots with MSB first.
25
FSY
I/O
Y Channel Frame Sync. Master Y Channel Frame Sync. Signal
followed by the first time slot of transmission. It can be either
input or output by initial setup sequence.
24
YOUT
O
Y Channel Data Out. Updated on the rising edge of CLKA
during selected time slots with MSB first.
2
RSTZ
I
Reset. Low active signal to force chip reset.
13
12
XTAL1/MCLK
XTAL2
I
O
Crystal In & Out. 14.318 MHz Crystal connected
∗∗∗.
17
CLKP
I/O
PCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
26
CLKA
I/O
ADPCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
18
15
11
10
9
8
5
1
SYNC1
SYNC2
SYNC3
SYNC4
SYNC5
SYNC6
SYNC7
SYNC8
O
O
O
O
O
O
O
O
Sync 1. Frame sync. for 1
st CODEC.
Sync 2. Frame sync. for 2
nd CODEC.
Sync 3. Frame sync. for 3
rd CODEC.
Sync 4. Frame sync. for 4
th CODEC.
Sync 5. Frame sync. for 5
th CODEC.
Sync 6. Frame sync. for 6
th CODEC.
Sync 7. Frame sync. for 7
th CODEC.
Sync 8. Frame sync. for 8
th CODEC.
4
3
TM1
TM0
I
I
TM1 &TM0 . Tie to Ground for normal operation.
7
6
A1
A0
I
I
A1 & A0. Address ID key for 3-wire serial port. If match, 3-wire
serial port can be enabled for configuration.
22
SDI/SDO
I/O
Serial Data In. Data for configuration on the fly by 3-wire serial
port. Sampled on the rising edge of SCLK with LSB first.
Serial Data Out. Output data after sending Read Memory
command by 3-wire serial port. Sampled on the rising edge of
SCLK with LSB first.
21
SCLK
I
Serial Clock. Used to write to the 3-wire serial port registers or
output data from 3-wire serial port registers.
23
SCSZ
I
Serial Port Chip Select. Low active to enable 3-wire serial port.
28
VDD
-
Power. 3.3 Volts.
14
19
Vss1
Vss2
-
-
Ground. 0 Volt.
∗∗∗For clock source other than 14.318MHz, please contact Atelic Systems.
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