поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

Preview PDF HTML

ES8288 датащи(PDF) 21 Page - Suzhou Everest Semiconductor Co. Ltd.

номер детали ES8288
подробное описание детали  Low Power Stereo Audio ADC
PDF  25 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  EVEREST [Suzhou Everest Semiconductor Co. Ltd.]
домашняя страница  http://www.everest-semi.com/en_index.html
Logo EVEREST - Suzhou Everest Semiconductor Co. Ltd.

ES8288 датащи(HTML) 21 Page - Suzhou Everest Semiconductor Co. Ltd.

Back Button ES8288 Datasheet HTML 17Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 18Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 19Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 20Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 21Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 22Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 23Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 24Page - Suzhou Everest Semiconductor Co. Ltd. ES8288 Datasheet HTML 25Page - Suzhou Everest Semiconductor Co. Ltd.  
Zoom Inzoom in Zoom Outzoom out
 21 / 25 page
background image
Everest Semiconductor
ES8288
Revision 6.0
November 2016
21
Stopband
0.5465
Fs
Passband Ripple
±0.05
dB
Stopband Attenuation
50
dB
Filter Frequency Response – Double Speed
Passband
0
0.4167
Fs
Stopband
0.5833
Fs
Passband Ripple
±0.005
dB
Stopband Attenuation
50
dB
Analog Input
Full Scale Input Level
AVDD/3.3
Vrms
Input Impedance
20
KΩ
Note
1. The value is measured used A-weighted filter.
8.4
Power Consumption Characteristics
PARAMETER
MIN
TYP
MAX
UNIT
Normal Operation Mode
DVDD=1.8V, PVDD=1.8V, AVDD=1.8V:
Record
DVDD=3.3V, PVDD=3.3V, AVDD=3.3V:
Record
9
30
mW
Power Down Mode
DVDD=1.8V, PVDD=1.8V, AVDD=1.8V
DVDD=3.3V, PVDD=3.3V, AVDD=3.3V
0.3
1.9
mW
8.5
Serial Audio Port Switching Specifications
PARAMETER
Symbol
MIN
MAX
UNIT
MCLK frequency
51.2
MHz
MCLK duty cycle
40
60
%
LRCK frequency
200
KHz
LRCK duty cycle
40
60
%
SCLK frequency
26
MHz
SCLK pulse width low
TSCLKL
15
ns
SCLK Pulse width high
TSCLKH
15
ns
SCLK falling to LRCK edge
TSLR
–10
10
ns
SCLK falling to SDOUT valid
TSDO
0
ns
SDIN valid to SCLK rising setup time
TSDIS
10
ns
SCLK rising to SDIN hold time
TSDIH
10
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com