PD780 datasheet(5/24 Pages) NEC

5 / 24 page

t-IEC

Architecture

The architecture includes a dual set of six 8-bit general

purpose registers and two a-bit accumulators and flag

registers. A flexible vectored interrupt structure is sup

ported by an 8-bit interrupt vector register that pro

vides the most-significant 8 bits of a pointer to a table

of vector addresses, while the requesting device

generates the least-significant 8 bits of the pointer.

Two 16-bit index registers enable the manipulation of

tabular data as well as facilitating code relocation.

Multilevel interrupts as well as virtually unlimited sub

routine nesting are supported by a 16-bit stack pointer

and complimentary 16-bit program counter, enhanc

ing the speed and efficiency of a wide variety of data

handling operations. Processing efficiency is addi

tionally supported by a special memory refresh regis

ter that enables automatic refreshing of all external

dynamic memory with minimal processor overhead.

The dual set of general-purpose registers may be used

as individual 8-bit registers or paired as 16-bit regis

ters. The dual register set (including a dual accumula

tor and flag register) not only allows more powerful

addressing and data transfer operations, but also per

mits programming in foreground/background mode

for vastly improved throughput.

Standard Test Conditions

The standard test conditions reference all voltages to

ground (0 V) and follow the convention that positive

current flows into the referenced pin. The listing of

AC parameters is based on a load capacitance of 50

pF unless explicitly stated otherwise. For every 50 pF

increase in load capacitance there is a 10 ns delay,

up to a maximum increase of 200 pF for the data bus

and 100 pF for the address bus and the bus control

lines.

The operating temperature range is: O°C to +70°C;

+4.75

V :s; Vee :s; +5.25 V.

Absolute Maximum Ratings

TA = 25°C

Oper

a ting tempe

ra tu

Stor

a ge temper

a ture

Volt

age on

Powe

r dissip

ation

Note:

(I) With respect to ground.

J.lPD780

DOC to+70°

-6 5°

to+ 15

0°

-0.3

to+7 V (1 )

1.5

Comment: Exposing the device to stresses above those listed in

Absolute Maximum Ratings could cause permanent damage. The

device is not meant to be operated under conditions outside the

limits described in the operational sections of this specification.

Exposure to absolute maximum rating conditions for extended

periods may affect device reliability.

Capacitance

TA = 25°C

Limns

Test

Parameter

Symbol

Min

Max

Unn

Condnlons

Clock ca p

acit

ance

pF le=1 MHz

Input ca pa cit

a nce

CIN

pF Unme

asured pins

Output

ca pa cit

ance CO

returned to ground.

DC Characteristics

TA =

Do C to +70oe; Vcc

+5 V ± 5% unless

otherwise specified

Parameter

Clock input

low volt

age

Clock input

high

volt

age

Input low volt

age

nput high

volt

age

Output

low volt

age

Output high volt

age

Power suppl

y ,..POlSO

Current

,..POlSO-l

Input

a ka ge cu

rrent

ree-st

a te output

a ka ge current in

flo

a t

Three-st

ate output

a ka ge current

in floa t

Da ta

bus le

a ka ge

rent in input

mode

Limits

Symbol

Min

"Jyp

VILC

-0.3

VIHC

Vee

-0.6

VIL

-0.3

VIH

2.0

VOL

VOH

2.4

Icc

lee

'll

'LDH

'LOL

ILO

Test

Max

Unn

Condnlons

0.45 V

Vee

+0.3

O.S

Vee

0.4

IOL=1

IOH= -250 ,..

rnA tC=400

200

te=250

;tA VIN=O toVee

;tA VOUT=2.4

Vee

-1

;tA VOUT=O.4 V

±10 ;tA O:sVIN

:sVce

4-7

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