AR8327-AL1A-R datasheet(148/394 Pages) ETC2

148 / 394 page

148 • AR8327/AR8327N Seven-port Gigabit Ethernet Switch

Atheros Communications, Inc.

148 • June 2011

COMPANY CONFIDENTIAL

3.6.26

PORT1_LEARN_LIMIT

Address 0x0674

SFT&HW RST

Table 3-132, “Port 1 Learn Limit Register,” on page 148 summarizes the PORT1_LEARN_LIMIT

Table 3-132.

Port 1 Learn Limit Register

7:6

R/W

DA_PRI_SEL_1

DA priority selected level for QOS.

There are five levels priority for QOS.

The highest is priority in packet

header.

The others are selected by these bits. If

these bits are set to zero, DA priority is

selected after header. If these bits are

set to n, DA priority is selected after the

priority set to n-1.

5:4

R/W

VLAN_PRI_SEL_1

3:2

R/W

IP_PRI_SEL_1

DA priority selected level for QOS.

1:0

R/O

RESERVED

IP priority selected level for QOS.

Bit

R/W

Inital

Value

Mnemonic

Description

Bit

R/W

Inital

Value

Mnemonic

Description

31:28

R/O

RESERVED

R/W

IGMP_LEARN_LIMIT_EN_1

1'b1: IGMP Learn Limit enable.

R/W

IGMP_LEARN_LIMIT_DROP_EN

1'b1: if IGMP GROUP ADDR is not in

ARL table or IGMP GROUP ADDR in

ARL but port member is not the source

port, packet should be dropped when

Learned MAC address counter is equal

to IGMP_JOIN_CNT_1

1'b0: if IGMP GROUP ADDR is not in

ARL table or IGMP GROUP ADDR in

ARL but port member is not the source

port, packet should be redirect to cpu

when Learned MAC address counter

is equal to IGMP_JOIN_CNT_1

25:16

R/W

IGMP_JOIN_CNT_1

HARDWARE JOIN IGMP. WHEN

JOIN NEW ENTRY OR NEW PORT TO

IGMP +1, LEAVE OR AGE -1

15:12

R/W

SA_LEARN_STATUS_1

IF LESS THAN 0X7, DYNAMIC CAN

BE FRESH TO SETTING VALUE AND

AGE

R/W

SA_LEARN_LIMIT_EN_1

1'b1: SA Learn Limit enable.

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