EPCQ32 datasheet(44/48 Pages) INTEL

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1.11.2. Pin-Out Diagram for EPCQ64, EPCQ128, EPCQ256, and EPCQ512/A

Devices

Figure 25.

AS x1 and AS x4 Pin-Out Diagrams for EPCQ64, EPCQ128, EPCQ256, and

EPCQ512/A Devices

VCC

N.C

nCS

DATA1

DCLK

DATA0

N.C.

N.C

GND

VCC

N.C

DATA3

VCC

N.C

nCS

DATA1

DCLK

DATA0

N.C.

N.C

GND

DATA2

N.C

AS x1

AS x4

Notes:

N.C pins must be left unconnected.

1.11.3. EPCQ Device Pin Description

Table 35.

EPCQ Device Pin Description

Nam

AS x1 Pin-Out

Diagram

AS x4 Pin-Out

Diagram

Pin Type

Description

Number

in 8-Pin

SOIC

Package

Number

in 16-

Pin SOIC

Package

Number

in 8-Pin

SOIC

Package

Number

in 16-

Pin SOIC

Package

DAT

I/O

For AS x1 mode, use this pin as an input signal pin to write

or program the EPCQ device. During write or program

operations, the data is latched on the rising edge of the

DCLK

signal.

For AS x4 mode, use this pin as an I/O signal pin. During

write or program operations, this pin acts as an input pin

that serially transfers data into the EPCQ device. The data is

latched on the rising edge of the DCLK signal. During read or

configuration operations, this pin acts as an output signal pin

that serially transfers data out of the EPCQ device to the

FPGA. The data is shifted out on the falling edge of the DCLK

signal.

During the extended quad input fast write bytes or extended

dual input fast write bytes operations, this pin acts as an

input pin that serially transfers data into the EPCQ device.

The data is latched on the rising edge of the DCLK signal.

During extended dual input fast read or extended quad input

fast read operations, this pin acts as an output signal pin

continued...

1. Quad-Serial Configuration (EPCQ) Devices Datasheet

CF52012 | 2018.06.01

Quad-Serial Configuration (EPCQ) Devices Datasheet

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