14
SOLOMON
SSD1815B
Rev 1.6
07/2002
given by:
• Display is turned OFF
• Default Display Display Mode, 132 x 64 + 1 Icon
Line
• Normal segment and display data column address
mapping (Seg0 mapped to Row address 00h)
• Read-modify-write mode is OFF
• Power control register is set to 000b
• Shift register data clear in serial interface
• Bias ratio is set to default, 1/9
• Static indicator is turned OFF
• Display start line is set to GDDRAM column 0
• Column address counter is set to 00h
• Page address is set to 0
• Normal scan direction of the COM outputs
• Contrast control register is set to 20h
• Test mode is turned OFF
• Temperature Coefficient is set to TC0
Note: Please find more explanation in the Applications Note at-
tached at the back of the specification.
Display Data Latch
This block is a series of latches carrying the display signal
information. These latches hold the data, which will be fed to the
HV Buffer Cell and Level Selector to output the required voltage
level.
The numbers of latches are given by: 132 + 65 = 197
HV Buffer Cell (Level Shifter)
HV Buffer Cell work as a level shifter which translates the
low voltage output signal to the required driving voltage. The out-
put is shifted out with an internal FRM clock which comes from
the Display Timing Generator. The voltage levels are given by
the level selector which is synchronized with the internal M sig-
nal.
Level Selector
Level Selector is a control of the display synchronization.
Display voltage levels can be separated into two sets and used
with different cycles. Synchronization is important since it se-
lects the required LCD voltage level to the HV Buffer Cell, which
in turn outputs the COM or SEG LCD waveform.
LCD Panel Driving Waveform
Figure 9 on page 16 is an example of how the Common and
Segment drivers may be connected to a LCD panel. The wave-
forms provided illustrates the desired multiplex scheme.
4. Bias Divider
If the output op-amp buffer option in Set Power Control Reg-
ister command is enabled, this circuit block will divide the regu-
lator output (VL6) to give the LCD driving levels (VL2 - VL5).
A low power consumption circuit design in this bias divider
saves most of the display current comparing to traditional de-
sign.
Stablizing Capacitors (0.01~0.47uF) are required to be con-
nected between these voltage level pins (VL2 - VL5) and VDD. If
the LCD panel loading is heavy, four additional resistors are sug-
gested to add to the application circuit as follows:
5. Bias Ratio Selection circuitry
SSD1815B can be software selected one of the bias ratios
from 1/4, 1/5, 1/6, 1/7, 1/8 and 1/9.
Since there will be slightly different in command pattern for
different members, please refer to Command Descriptions sec-
tion of this data sheet.
6. Self adjust temperature compensation circuitry
This block provides 4 different compensation settings to sat-
isfy various liquid crystal temperature grades by software con-
trol. Default temperature coefficient (TC) setting is TC0.
Graphic Display Data RAM (GDDRAM)
The GDDRAM is a bit mapped static RAM holding the bit
pattern to be displayed. The size of the RAM is 132 x 65 = 8580
bits. Figure 8 on page 15 is a description of the GDDRAM ad-
dress map.
For mechanical flexibility, re-mapping on both Segment and
Common outputs can be selected by software.
For vertical scrolling of the display, an internal register stor-
ing display start line can be set to control the portion of the RAM
data to be mapped to the display. Figure 8 on page 15 shows the
case in which the display start line register is set to 38h.
For those GDDRAM out of the display common range, they
could still be accessed, for either preparation of vertical scrolling
data or even for the system usage.
Reset Circuit
This block includes Power On Reset circuitry and the hard-
ware reset pin, RES. Both of these having the same reset func-
tion. Once RES receives a negative reset pulse, all internal
circuitry will start to initialize. Minimum pulse width for complet-
ing the reset sequence is 5us. Status of the chip after reset is
Figure 7 Connections for heavy loading applications
SSD1815B
V DD
V L2
VL3
VL4
VL5
VL6
R3
R1
R2
R4
VDD
C5
C4
C3
C2
C1
Remark: 1. C1 ~ C5 = 0.01 ~ 0.47uF
2. R1 ~ R4 = 100k~ 1M
Ω
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