APL5331 datasheet(12/20 Pages) ANPEC

12 / 20 page

 ANPEC Electronics Corp.

Rev. A.8 - Oct., 2003

APL5331

www.anpec.com.tw

A capacitor of 1

µF (ceramic chip capacitor) or greater

(aluminum electrolytic capacitor) is recommended to

connect near VCNTL pin. For VIN pin, an aluminum

electrolytic capacitor (>50

µF) is recommended. It is

not necessary to use low-ESR capacitors.

Layout and Thermal Consideration

The input capacitors for VIN and VCNTL pins are

normally placed near each pin for good

performances. Ceramic decoupling capacitors at

output must be placed as close to the load to reduce

the parasitic inductors of traces. It is also recom-

mended that the APL5331 and output capacitors are

placed near the load for good load regulation and

load transient response. The negative pins of the in-

put and output capacitors and the GND pin of the

APL5331 should connect to analog ground plane of

the load.

See figure 1. The SOP-8-P utilizes a bottom thermal

pad to minimize the thermal resistance of the package,

making the package suitable for high current

applications. The thermal pad is soldered to the top

ground pad and is connected to the internal or bot-

tom ground plane by several vias. The printed circuit

board (PCB) forms a heat sink and dissipates most

of the heat into ambient air. The vias are recom-

mended to have proper size to retain solder, helping

heat conduction.

Thermal resistance consists of two main elements,

?JC (junction-to-case thermal resistance) and ?CA

(case-to-ambient thermal resistance).

?JC is speci-

fied from the IC junction to the bottom of the thermal

pad directly below the die.

?CA is the resistance from

the bottom of thermal pad to the ambient air and it

includes

?CS (case-to-sink thermal resistance) and

?SA (sink-to-ambient thermal resistance). The speci-

fied path for heat flow is the lowest resistance path

and it dissipates majority of the heat to the ambient

air. Typically,

?CA is the dominant thermal resistance.

Therefore, enlarging the internal or bottom ground

plane reduces the resistance

?CA . The relationship

between power dissipation and temperatures is the

following equation :

PD = (TJ - TA) /

?JA

where,

PD : Power dissipation

TJ : Junction Temperature

TA : Ambient Temperature

?JA : Junction-to-Ambient Thermal Resis-

tance

T herm a l

pad

Di e

To p

gr ound

pad

Prin te d

circuit

boar d

In te rnal

gr ound

plane

Via s

Ambi ent

Air

118 mi l

102 mi l

SO P-8-P

Figure 2 shows a board layout using the SOP-8-P

package. The demo board is made of FR-4 material

and is a two-layer PCB. The size and thickness are

65mm* 65mm and 1.6mm. An area of 140mil*105mil

on the top layer is use as a thermal pad for the

APL5331 and this is connected to the bottom layer

by vias. The bottom layer using 2 oz. copper acts as

the ground plane for the system. The PCB and all

components on the board form a heat sink. The

?JA

of the APL5331(SOP-8-P) mounted on this demo

board is about 37oC/W in free air. Assuming the

TA=25oC and the maximum TJ=150oC (typical thermal

limit temperature), the maximum power dissipation is

calculated as :

Figure 1 Package Top and side view

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