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STV0974 датащи(PDF) 55 Page - STMicroelectronics |
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STV0974 датащи(HTML) 55 Page - STMicroelectronics |
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55 / 69 page ![]() Electrical characteristics STV0974 55/61 5.5 AC electrical characteristics 5.5.1 CLK 5.5.2 I2C slave timing Table 38: CLK electrical characteristics ( Figure 30) Symbol Parameter Min. Typ. Max. Unit VCDC DC coupled square wave voltage 1.7 1.8 1.9 Vp-p fCLK Clock frequency input 6.5 13 26 MHz Figure 30: CLK electrical characteristics Table 39: I2C slave timing ( Figure 31) Symbol Parameter Min. Typ. Max. Unit fSCL SCL clock frequency 400 kHz tLOW Clock pulse width low 1.3 µs tHIGH Clock pulse width high 0.6 µs tSP Pulse width of spikes which are suppressed by the input filter 50 ns tBUF Bus free time between transmissions 1.3 µs tHD.STA Start hold time 0.6 µs tSU.STA Start set-up time 0.6 µs tHD.DAT Data in hold time 0.15 0.9 µs tSU.DAT Data in set-up time 100 ns tR SCL / SDA rise timea a. Measured from 0.1 to 0.9 or 0.9 to 0.1 VDD and with 4.7 k pull-up resistor and 100pF maximum capacitance on both SDA and SCL. 300 ns tF SCL / SDA fall timea 300 ns tSU.STO Stop set-up time 0.6 µs tDH Data out hold-time 0 0.6 0.9 µs 1/fCLK VCDC |
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