CS5397 datasheet(15/40 Pages) CIRRUS

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CS5396 CS5397

DS229PP2

Master Clock - Control Port Mode

The master clock is the clock source for the delta-

sigma modulator sampling (MCLKA) and digital

filters (MCLKD). The required MCLKA/D fre-

quency is determined by the desired Fs and the cho-

sen Oversampling Mode. Table 2 shows some

common master clock frequencies.

× vs. 128× Oversampling Modes

The CS5396/97 can operate in a 64

× Oversampling

Mode with a 256

× master clock (MCLKA/D) at a

maximum sample rate of 100 kHz. The device can

also operate in a 128

× Oversampling Mode with a

512

× master clock (MCLKA/D) where the maxi-

mum Fs is 50 kHz. Notice that the required master

clock is 24.576 MHz for Fs equal to either 48 kHz

in the 128

× Oversampling Mode or 96 kHz in the

× Oversampling Mode. The sampling mode is

set via the control register which alters the decima-

tion ratio of the digital filter. The 64

× Oversam-

pling Mode is the default mode. Table 2 shows

some common clock frequencies for both modes.

Refer to Appendix A for additional discussion of

× vs. 128× Oversampling Modes.

Table 2. Common Clock Frequencies

Serial Data Interface - Control Port Mode

The CS5396/97 supports two serial data formats

which are selected via the control register. The dig-

ital output format determines the relationship be-

tween the serial data, left/right clock and serial

clock. Figures 4 - 7 detail the interface formats.

The serial data interface is accomplished via the se-

rial data outputs; SDATA1 and SDATA2, serial

data clock, SCLK, and the left/right clock, LRCK.

The serial nature of the output data results in the left

and right data words being read at different times.

However, the samples within an LRCK cycle repre-

sent simultaneously sampled analog inputs.

Serial Data - Control Port Mode

The serial data block is presented in 2’s-comple-

ment format with the MSB-first. The data is clocked

from SDATA1 and SDATA2 by the serial clock

and the channel is determined by the Left/Right

clock. The full precision 24 bit data is available on

SDATA1 and the output from the low group delay

is available on SDATA2.

The serial data can be followed by 8 Peak Signal

Level, PSL, bits as shown in Figures 4 - 7 if the

PKEN bit is set. Refer to the Dual Audio Output

section of this data sheet for further discussion of

SDATA1 and SDATA2 options.

Serial Clock - Control Port Mode

The serial clock shifts the digitized audio data from

the internal data registers via SDATA1 and

SDATA2. SCLK is an output in Master Mode

where internal dividers will divide the master clock

by 4 to generate a serial clock which is 64

× Fs in

the 64

× Oversampling Mode. In the 128× Over-

sampling Mode, internal dividers will divide

MCLKA/D by 4 to generate a SCLK which is 128

Fs. In Slave Mode, SCLK is an input with a serial

clock typically between 48

× and 128× Fs. It is rec-

ommended that SCLK be equal to 64

× in the 64×

Oversampling Mode and equal to 128

× in the 128×

Oversampling Mode to avoid possible system per-

formance degradation due to interference effects.

Left/Right Clock -Control Port Mode

The Left/Right clock, LRCK, determines which

channel, left or right, is to be output on SDATA1

LRCK

(kHz)

Over-

sampling

MCLKA/D

(MHz)

SCLK

(MHz)

8.192

2.048

44.1

11.2896

2.822

12.288

3.072

128

16.384

4.096

44.1

128

22.5792

5.6448

128

24.576

6.144

16.384

4.096

88.2

22.5792

5.6448

24.576

6.144

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