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GC4016 датащи(PDF) 9 Page - Texas Instruments |
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GC4016 датащи(HTML) 9 Page - Texas Instruments |
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9 / 83 page ![]() © GRAYCHIP,INC. - 4 - August 27, 2001 GC4016 MULTI-STANDARD QUAD DDC CHIP DATA SHEET REV 1.0 This document contains information which may be changed at any time without notice 3.2 INPUT FORMAT The chip accept five input formats: (1) Four input ports of 14 bit data, (2) Three input ports of 16 bit data, (3) Two input ports of 14 bit low voltage differential data, (Contact Graychip for more information) (4) Three ports of 12 bit with 3 bit exponent floating point data, and (5) Three ports of multiplexed, dual channel, 12 bit with 3 bit exponent floating point data The 12, 14 and 16 bit input words are in a two’s complement format. The MSB_POL control bit in address 27 of the channel control pages can be used to convert offset binary data to the desired two’s complement format. The 3 bit exponent in the floating point format is an unsigned integer ranging from 0 to 7. All inputs are converted to the internal 19 bit format at the input to each channel. The 14 and 16 bit input words are put into the upper 14 and 16 bits respectfully of the 19 bit word. The unused LSBs are cleared. The 12 bit floating point word is shifted down and sign extended by the amount specified by the 3 bit exponent and then put into the MSBs of 19 bit word. A crossbar switch allows the user to route any input source to any downconverter channel. Table 1 shows the suggested control register settings required for each input mode. See Section 5.6 for detailed descriptions of each control setting Table 1: Input Mode Controls Control Address in Channel Control Pages 7, 15, 23 and 31 14 bit mode 16 bit mode 14 bit differential mode 12 + 3 bit exponent mode Multiplexed 12 + 3 bit exponent mode SHIFT 1 16 4 to 7 4 to 7 4 to 7 unused unused USE_SHIFT 16 1 1 1 0 0 MIX20B1 23 1 1 1 0 0 INPUT_SEL 3 27 0,1,2,3 0,1,2 4,5 0,1,2 0,1,2 SEL_AB 27 0 0 0 0 0 or 1 INPUT_MODE 27 0 1 0 2 2 DIFF_IN 4 (Global Page) 0 0 1 0 0 NOTES: 1. SHIFT is normally left at 4, see Section 3.3.3 for details. 2. For decimations over 3104, MIX20B should be 0 to allow SHIFT to be less than 4, see Section 3.3.3. 3. INPUT_SEL is used to select the input port used by each channel, 0=port A, 1=portB, 2=port C, 3=portD. 3.3 THE DOWN CONVERTERS Each down converter contains an NCO and a mixer to quadrature down convert the signal to baseband, followed by a 5 stage Cascade Integrate Comb (CIC)1 filter and two stages of decimate by two filtering to isolate the desired signal. The signal is then sent to a resampler which can increase or decrease the final output sample rate to match the post-processing requirements for baud rate sampling or oversampling. A block diagram of the channel is shown in Figure 4. The INPUT FORMAT circuit converts the selected input data into the 19 bit format described in Section 3.2. The ZERO PAD function allows the user to clock the chip at a higher rate than the input sample rate. The NCO/Mixer circuit tunes the desired center frequency down to DC where it is low pass filtered by the CIC, CFIR, PFIR and Resampler filters. The CIC filter reduces the sample rate by a programmable factor ranging from 8 to 4,096. The CIC outputs are followed by a coarse gain stage and then followed by two stages of decimate by 2 filtering. The coarse gain circuit allows the user to boost the gain of weak signals up to 42 dB in 6 dB steps. The first stage of the two stage filter is a 21 tap decimate by 2 filter (CFIR) with user programmable tap weights. The 21 tap symmetrical lowpass filter is downloaded into the chip as 12 words, 16 bits each. This filter is typically programmed to decimate by two, while 1. Hogenhauer, An Economical Class of Digital Filters for Decimation and Interpolation, IEEE transactions on ASSP, April 1981. |
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