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September 2004

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5V TOLERANT INPUTS

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HIGH SPEED:

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POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

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SYMMETRICAL OUTPUT IMPEDANCE:

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PCI BUS LEVELS GUARANTEED AT 24 mA

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BALANCED PROPAGATION DELAYS:

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OPERATING VOLTAGE RANGE:

Retention)

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PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 138

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LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

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ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LCX138 is a low voltage CMOS 3 TO 8

LINE DECODER (INVERTING) fabricated with

sub-micron silicon gate and double-layer metal

and high speed 3.3V applications; it can be

interfaced to 5V signal environment for inputs.

If the device is enabled, 3 binary select inputs (A,

B and C) determine which one of the outputs will

go low. If enable input G1 is held low or either G2A

or G2B is held high, the decoding function is

inhibited and all the 8 outputs go to high.

Three enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All

inputs

and

outputs

are

equipped

with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

74LCX138

LOW VOLTAGE CMOS 3 TO 8 LINE DECODER (INV.)

WITH 5V TOLERANT INPUTS

Figure 1: Pin Connection And IEC Logic Symbols

Table 1: Order Codes

PACKAGE

T & R

SOP

74LCX138MTR

TSSOP

74LCX138TTR

TSSOP

SOP

Rev. 4