Rev. A.8 - Oct., 2003
HPL5331
2
Copyright HIPAC Semiconductor, Inc.
www.hipacsemi.com
Package Code
K : SOP-8
KA : SOP-8-P
U5 : TO-252-5
G5 : TO-263-5
Temp. Range
C : 0 to 70
oC
Handling Code
TR : Tape & Reel
Lead Free Code
L : Lead Free Device
Blank : Original Device
HPL5331
Handling Code
Temp. Range
Package Code
HPL5331
XXXXX
HPL5331KC-TR :
HPL5331KAC-TR :
XXXXX - Date Code
HPL5331
XXXXX
HPL5331U5C-TR :
HPL5331G5C-TR :
XXXXX - Date Code
Lead Free Code
Ordering and Marking Information
Pin Description
PIN NAME
I/O
DESCRIPTION
VIN
I
Main power input pin. Connect this pin to a voltage source and an input
capacitor. The HPL5331 sources current to VOUT pin by controlling the upper
NPN pass transistor, providing a current path from VIN pin.
GND
O
Power and signal ground. Connect this pin to system ground plane with shortest
traces. The HPL5331 sinks current from VOUT pin by controlling the lower NPN
pass transistor, providing a current path to GND pin. This pin is also the ground
path for internal control circuitry.
VCNTL
I
Power input pin for internal control circuitry. Connect this pin to a voltage source,
providing a bias for the internal control circuitry. A bypass capacitor is usually
connected near this pin.
VREF
I
Reference voltage input and active-low shutdown control pin. Apply a voltage to
this pin as a reference voltage for the HPL5331. Connect this pin to a resistor
divider, between VIN and GND, and a capacitor for soft-start and filtering noise
purposes. Applying and holding this pin low by an open-drain transistor to shut
down the output.
VOUT
O
Output pin of the regulator. Connect this pin to load. Output capacitors
connected this pin improves stability and transient response. The output voltage
tracks the reference voltage and is capable of sourcing or sinking current up to
3A.
Block Diagram
VC NTL
C urrent
Lim it
GND
VOUT
VIN
VC NTL
VREF
Cu rre nt
Lim it
Th erm a l
Lim it
Vo lt ag e
R egulation
S hutdow n
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