2-Wire Serial 4K-Bit (512 x 8) CMOS Electrically Erasable PROM

AM24LC04

Anachip Corp.

www.anachip.com.tw

Rev. A2 Oct 20, 2003

8/12

ATC

8

1

9

ACKNOWLEDGE

START

Figure 3. Acknowledge Response from Receiver

SCL FROM MASTER

DATA OUTPUT FROM

TRANSMITTER

DATA OUTPUT FROM

RECEIVER

DATA n

BYTE

ADDRESS

SLAVE

ADDRESS

A

C

K

A

C

K

A

C

K

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

Figure 4. Byte Write for Data

S

P

STOP

START

A

C

K

A

C

K

A

C

K

A

C

K

Figure 5. Page Write for Data

S

P

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

DATA n

BYTE

ADDRESS n

SLAVE

ADDRESS

STOP

START

DATA n+15

DATA

P

A

C

K

Figure 6. Current Address Read for Data

s

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

SLAVE

ADDRESS

STOP

START

A

C

K

NO

P

S

S

A

C

K

A

C

K

A

C

K

DATA n

Figure 7. Random Read for Data

BYTE

ADDRESS n

SLAVE

ADDRESS

STOP

START

SLAVE

ADDRESS

START

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

A

C

K

NO

S

A

C

K

DATA n

A

C

K

DATA n+1

A

C

K

DATA n+x

P

Figure 8. Sequential Read for Data

BUS ACTIVITY

SLAVE

SDA

LINE

BUS ACTIVITY

MASTER

SLAVE

ADDRESS

START

STOP

A

C

K

NO