Conceptual

uP9616

13

uP9616-DS-C3202, Feb. 2017

www.upi-semi.com

Application Information

Layout Guidelines For uP9616PDYA:

1. Arrange the power components to reduce the AC loop size consisting of C

2. The input decoupling ceramic capacitor 1uF must be placed closest to the VIN (Pin 5) and Exposed Pad GND plane

through vias or a short and wide path.

3. Return SENSE+ (PIN 9) to signal GND pin, and connect the signal GND to power GND at a single point for best noise

immunity. Connect exposed pad to power ground copper area with copper and vias.

4. Apply copper plane to Exposed Pad GND for best heat dissipation and noise immunity. The exposed pad is the main

path for heat convection and should be well-soldered to the PCB for best thermal performance.

5. Use a short trace connecting the bootstrap capacitor C

circuit.

6. Use a short trace connecting R-C to LX (Pin 6,7) and Exposed Pad GND Plane to form a Snubber Circuit.

7. The LX (Pin 6,7) pad is the noise node switching from VIN (Pin 5) to GND. LX node copper area should be minimized

to reduce EMI and should be isolated from the rest of circuit for good EMI and low noise operation.

8. The CC1 (Pin 4), CC2 (Pin 5), D+ (Pin 2) pad and D- (Pin 1) pad of the uP9616 are the USB detect data line input

node, the CC1, CC2, D+ and D- Pin of the via or trace area should be isolated using 0.96mm space to prevent direct

contact with VIN area components which may cause voltage of CC1, CC2, D+ and D- pins to exceed maximum

rating of 6V.

uP9616PDYA

VIN Plane

SENSE+

Plane

+

+

5V

D+

D-

GND

USB Connector

SENSE-

Plane

GND Plane

GND Plane

Via to D+

Via to D-

Via to GND Plan

-

-

Exposed

Pad (GND)

5

4

3

2

9

8

7

6

1

10

Via to CC2

Via to CC1

CC1

CC2