8535AG-21

www.icst.com/products/hiperclocks.html

REV. A OCTOBER 20, 2004

6

Integrated

Circuit

Systems, Inc.

ICS8535-21

Input/Output Additive Phase Jitter,

Integration Range: 12KHz - 20MHz at

156.25MHz = 0.03ps (typical)

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-160

-170

-180

-190

1k

10k

100k

1M

10M

100M

The spectral purity in a band at a specific offset from the fun-

damental compared to the power of the fundamental is called

the

dBc Phase Noise. This value is normally expressed using

a Phase noise plot and is most often the specified plot in many

applications. Phase noise is defined as the ratio of the noise

power present in a 1Hz band at a specified offset from the

fundamental frequency to the power value of the fundamental.

This ratio is expressed in decibels (dBm) or a ratio of the power

As with most timing specifications, phase noise measurements

have issues. The primary issue relates to the limitations of the

equipment. Often the noise floor of the equipment is higher

than the noise floor of the device. This is illustrated above. The

in the 1Hz band to the power in the fundamental. When the

required offset is specified, the phase noise is called a

dBc

value, which simply means dBm at a specified offset from the

fundamental. By investigating jitter in the frequency domain,

we get a better understanding of its effects on the desired ap-

plication over the entire time record of the signal. It is math-

ematically possible to calculate an expected bit error rate given

a phase noise plot.

device meets the noise floor of what is shown, but can actually

be lower. The phase noise is dependant on the input source

and measurement equipment.