39
Preliminary
Version: DM9161A-DS-P04
Jan.19,2005
9.4.6 100BASE-TX Transmit Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tTXc
TXCLK Cycle Time
39.998
40
40.002
ns
50ppm
tTXh, tTXl
TXCLK High/Low Time
16
20
24
ns
tTXs
TXD [0:3], TXEN, TXER Setup To TXCLK High
12
-
-
ns
tTXh
TXD [0:3], TXEN, TXER Hold From TXCLK High
0
-
-
ns
tTXOD
TXCLK to Output Delay
25
ns
t1
TXEN Sampled To CRS Asserted
-
4
-
BT
t2
TXEN Sampled To CRS De-asserted
-
4
-
BT
tTXpd
TXEN Sampled To TX+/- Out (Tx Latency)
-
8
-
BT
tTXr/f
100TX Driver Rise/Fall Time
3
4
5
ns
90% To 10%, Into
100ohm Differential
Note 1. Typical values are at 25℃and are for design aid only; not guaranteed and not subject to production testing.
9.4.7 100BASE-TX Transmit Timing Diagram
TXCLK
tTX
h
t2
tTX
S
t1
tTX
pd
tTX
r/f
TXD [0:3],
TXEN, TXER
CRS
100TX+/-
tTXc
tTXh
tTXOD
9.4.8 100BASE-TX Receive Timing Parameters
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tRXc
RXCLK Cycle Time
39.998
40
40.002
50ppm
TRXh, tRXl
RXCLK High/Low Time
16
20
24
tRXs
RXD [0:3], RXDV, RXER Setup To RXCLK High
10
-
-
ns
tRXh
RXD [0:3], RXDV, RXER Hold From RXCLK High
10
-
-
ns
tRXpd
RX+/- In To RXD [0:3] Out (Rx Latency)
-
15
-
BT
t1
CRS Asserted To RXD [0:3], RXDV, RXER
-
4
-
BT
t2
CRS De-asserted To RXD [0:3], RXDV, RXER
-
0
-
BT
t3
RX+/- In To CRS Asserted
10
-
14
BT
t4
RX+/- Quiet To CRS De-asserted
14
-
18
BT
t5
RX+/- In To COL De-Asserted
14
-
18
BT
1. Typical values are at 25℃and are for design aid only; not guaranteed and not subject to production testing.
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