MCP6041 datasheet(12/32 Pages) MICROCHIP

12 / 32 page

MCP6041/2/3/4

DS21669B-page 12

2002 Microchip Technology Inc.

macro model and bench testing to adjust RISO until the

frequency response peaking is reasonable. Use the

smallest reasonable value.

FIGURE 3-2:

Amplifier circuit for heavy

capacitive loads.

3.6

The MCP6043 Chip Select (CS)

Option

The MCP6043 is a single amplifier with a chip select

(CS) option. When CS is pulled high, the supply current

drops to 20 pA (typ) and goes through the CS pin to

VSS. When this happens, the amplifier is put into a high

impedance state. By pulling CS low, the amplifier is

enabled. If the CS pin is left floating, the amplifier will

not operate properly. Figure 3-3 shows the output volt-

age and supply current response to a CS pulse.

FIGURE 3-3:

Timing Diagram for the CS

function on the MCP6043 op amp.

3.7

Layout Considerations

Good PC board layout techniques will help you achieve

the performance shown in the specs and Typical Per-

formance Curves. It will also assist in minimizing Elec-

tro-Magnetic Compatibility (EMC) issues.

3.7.1

SURFACE LEAKAGE

In applications where low input bias current is critical,

PC board surface leakage effects and signal coupling

from trace to trace need to be considered.

Surface leakage is caused by a difference in voltage

between traces, combined with high humidity, dust or

other contamination on the board. Under low humidity

conditions, a typical resistance between nearby traces

is 1012

Ω. A 5 V difference would cause 5 pA of current

to flow; this is greater than the input current of the

MCP6041/2/3/4 family at 25°C (1 pA, typ).

The simplest technique to reduce surface leakage is

using a guard ring around sensitive pins (or traces).

The guard ring is biased at the same voltage as the

sensitive pin or trace. Figure 3-4 shows an example of

a typical layout.

FIGURE 3-4:

Example of Guard Ring

layout.

Circuit schematics for different guard ring implementa-

tions are shown in Figure 3-5. Figure 3-5A biases the

guard ring to the input common mode voltage, which is

most effective for non-inverting gains, including unity

gain. Figure 3-5B biases the guard ring to a reference

voltage (VREF, which can be ground). This is useful for

inverting gains and precision photo sensing circuits.

FIGURE 3-5:

Two possible guard ring

connection strategies to reduce surface leakage

effects.

VIN

RISO

VOUT

MCP604X

VIL

Hi-Z

tON

VIH

tOFF

VOUT

IVDD

20 pA, typ

Hi-Z

IVSS

ICS

5 pA, typ

5pA, typ

20 pA, typ

0.6 µA, typ

5 pA, typ

0.6 µA, typ

5pA, typ

Guard Ring

VSS

IN-

IN+

VREF

MCP604X

Figure 3-5A

Figure 3-5B

VDD

VREF

MCP604X

VDD

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