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71321LA55TFGI датащи(PDF) 12 Page - Integrated Device Technology |
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71321LA55TFGI датащи(HTML) 12 Page - Integrated Device Technology |
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12 / 18 page ![]() 6.42 IDT71321SA/LA and IDT71421SA/LA High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges 12 tWC tWP tDW tDH tBDD tDDD tBDA tWDD ADDR"B" DATAOUT"B" DATAIN"A" ADDR"A" MATCH VALID MATCH VALID R/W "A" BUSY"B" tAPS (1) 2691 drw 10 tBAA T im ing Wa ve for m of Writ e w it h Por t -t o-Por t Re a d a nd BUSY(2,3,4) NOTES: 1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT71421). 2. CEL = CER = VIL 3. OE = VIL for the reading port. 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". NOTES: 1. tWH must be met for both BUSY input (IDT71421, slave) or output (IDT71321, Master). 2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH. 3. tWB is only for the slave version (IDT71421). 4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A". T im ing Wa ve for m of Writ e w it h BUSY(4) BUSY"B" 2691 drw 11 R/W"A" tWP tWH tWB R/W"B" (2) (1) (3) , |
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