HT95C30P datasheet(16/42 Pages) HOLTEK

16 / 42 page

HT95L100/10P

Rev. 0.10

October 1, 2002

Preliminary

Timer/Event Counter

Two timer/event counters (TMR0, TMR1) are imple-

mented in the telephone controller series. The

Timer/Event Counter 0 and Timer/Event Counter 1 con-

tain 16-bits programmable count-up counter and the

clock may come from an external source or internal

source. For TMR0 internal source is instruction clock

(system clock/4). For TMR1 internal source is 32768Hz.

Using the 32768Hz clock or instruction clock, there is

only one reference time-base. The external clock input

allows the user to count external events, measure time

intervals or pulse width, or generate an accurate time

base.

There are 3 registers related to Timer/Event Counter 0;

TMR0H, TMR0L, TMR0C. Writing TMR0L only writes

the data into a low byte buffer, but writing TMR0H simul-

taneously writes the data along with the contents of the

low byte buffer into the Timer/Event Counter 0 preload

ing TMR0L will keep the Timer/Event Counter 0 preload

Reading TMR0H latches the TMR0L into the low byte

buffer to avoid a false timing problem. Reading TMR0L

returns the contents of the low byte buffer. In other

words, the low byte of the Timer/Event Counter 0 can

not be read directly. It must read the TMR0H first to

make the low byte contents of Timer/Event Counter 0 be

latched into the buffer.

There are 3 registers related to the Timer/Event Counter

1; TMR1H, TMR1L, TMR1C. The Timer/Event Counter

1 operates in the same manner as the Timer/Event

Counter 0.

The TMR0C is the Timer/Event Counter 0 control regis-

ter, which defines the Timer/Event Counter 0 options.

The Timer/Event Counter 1 has the same options as the

T M 1

T M 0

I N T / T M R 1

T M R 0

T E

T M 1

T M 0

T O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

T i m e r / E v e n t C o u n t e r 0 / 1

P r e l o a d R e g i s t e r

T i m e r / e v e n t

C o u n t e r 0 / 1

D a t a B u s

R e l o a d

O v e r f l o w

t o I n t e r r u p t

T i m e r 0 : I n s t r u c t i o n c l o c k ( s y s t e m c l o c k / 4 )

T i m e r 1 : 3 2 7 6 8 H z

L o w B y t e B u f f e r

Timer/Event Counter 0/1

Label

Bits

R/W

Function

TMR0C

(0EH)

TMR1C

(11H)

0~2

Unused bit, read as

²0²

To define the TMR0/TMR1 active edge of timer

For event count or Timer mode

(0=active on low to high; 1=active on high to low)

For pulse width measurement mode

(0=measures low pulse width; 1=measures high pulse width)

TON

To enable/disable timer counting (0=disabled; 1=enabled)

5RO

Unused bit, read as

²0²

TM0

TM1

To define the operating mode

Bit 7, 6=01, Event count mode (external clock)

Bit 7, 6=10, Timer mode

Bit 7, 6=11, Pulse width measurement mode

Bit 7, 6=00, Unused

Bits

R/W

Function

TMR0H (0CH)

0~7

Timer/Event Counter 0 higher-order byte register

TMR0L (0DH)

0~7

Timer/Event Counter 0 lower-order byte register

TMR1H (0FH)

0~7

Timer/Event Counter 1 higher-order byte register

TMR1L (10H)

0~7

Timer/Event Counter 1 lower-order byte register

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