IC-MSC datasheet(21/35 Pages) ICHAUS

21 / 35 page

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iC-MSC SIN/COS SIGNAL CONDITIONER

WITH FAIL-SAFE 1 Vpp LINE DRIVER

Rev A2, Page 21/35

TEST MODE

iC-MSC switches to test mode if a voltage larger

than VTMon is applied to pin ERR (precondition:

TMODE(0) = 1). In response iC-MSC transmits its con-

figuration settings as current-modulated data using I/O

pin ERR either directly from the RAM (for TMEM = 1)

or after re-reading the EEPROM (for TMEM = 0). If the

voltage at pin ERR falls below VTMoff, test mode is

terminated and data transmission aborted.

The clock rate for the data output is determined by

ENFAST. Two clock rates can be selected: 780 ns for

ENFAST = 1 or 3.125 µs for ENFAST = 0 (see Electri-

cal Characteristics, D08, for clock frequency and toler-

ances).

Data is output in Manchester code via two clock pulses

per bit. To do this the lowside current source switches

between a Z state (OFF = 0 mA) and an L state (ON =

2 mA).

The bit information lies in the direction of the current

source switch:

Zero bit: change of state Z → L (OFF to ON)

One bit: Change of state L → Z (ON to OFF)

Transmission consists of a start bit (a one bit), 8 data

bits and a pause interval in Z state (the timing is identi-

cal to the communication with an EEPROM via the I2C

interface).

Example: byte value = 1000 1010

Transmission including the start bit: 1 1000 1010

In Manchester code: LZ LZZL ZLZL LZZL LZZL

Decoding of the data stream:

ZZZZZZ LZ LZ ZL ZL ZL LZ ZL LZ ZL ZZZZZZ

Pause 1 1 0 0 0 1 0 1 0 Pause

If test mode is quit with TMODE = 0x00, iC-MSC contin-

ues operation without any interruption.

If test mode is quit with TMODE > 0x00, then iC-MSC

again reads out its configuration from the EEPROM

accessible at the device ID stored in DEVID(6:0) of ad-

dress 0x00.

In TMODE = 0x03 the EEPROM is read completely; in

all other cases only the address range 0x00 to 0x21 is

read to keep the configuration time for device testing

short.

Note: The device ID for the EEPROM can be en-

tered in register DEVID(6:0) (address 0x00), from which

iC-MSC will take its configuration after exiting test mode.

The DEVID(6:0) stored therein is then accepted.

TMODE

Addr. 0x15, bit 7:6

Code

Function during test

mode

Function following test

mode

Normal operation

TMEM = 0:

Transmission of

EEPROM data

0x1B-0x7F:

OEM data (4 bytes) and

registered errors

Repeated read out of

EEPROM

(MODE = 0: 0x00-0x7F)

(MODE > 0: 0x00-0x21)

TMEM = 1:

Transmission of

RAM data 0x3B-0x43:

OEM data (4 bytes) and

current errors

Normal operation

Repeated read out of

EEPROM

(MODE = 0: 0x00-0x7F)

(MODE > 0: 0x00-0x21)

Transmission of

EEPROM data

(0x00-0x7F)

Repeated read out of

EEPROM

(0x00-0x7F)

Table 17: Test Mode Functions

TMEM

Addr. 0x18, bit 7

Code

Memory selection

EEPROM

iC-MSC RAM (ENSL = 1)

Table 18: Test Mode Memory Selection

DATA_ON

AD8029

U22-S

M21

100nF

LM393

R27

dra_mq1d_error_schem

NDIS

max. 5V

GND

U22-A

C25

365k

LM393

U23-B

100nF

R22

2N7002

C21

LM393

U21

LM285

R28

51k

100nF

R23

AD8029

C23

470

LL4148

C24

M22

IRLML6401

100pF

U23-A

LM393

C22

100nF

R28

U23-S

R27

R25

100k

R25

100nF

C26

ERR

JP4

C26

M21

2N7002

VDD

DATA_ON

LM393

U23-B

100k

R26

M22

LM285

LM393

C23

100k

R22

365k

AD8029

U22-A

C24

475k

R21

U22-S

AD8029

U21

51k

100nF

D21

U23-S

R24

DATA_OUT

100nF

C21

JP4

470

R24

R21

475k

LL4148

D21

100pF

C25

100nF

IRLML6401

R26

100k

R23

U23-A

100nF

DATA_OUT

100nF

C22

Figure 1: Example circuit for the decoding and con-

version of the current-modulated signals to

logic levels.

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