FPD85308 datasheet(9/31 Pages) NSC

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Functional Description

FPD-LINK Receiver

The LVDS based FPD-Link Receiver receives inputs video

data and control timing. Four LVDS channels plus clock

provide 24-bit color. Three LVDS channels can be used for

18-bit color.

The video data is regenerated to a parallel data stream and

routed to the 8 to 6 Bit Translator. The General Purpose

Outputs (GPOs) continue outputting the programmed control

sequence at a reduced frame rate. RSTZ initialized the chip

with the default register values. EEPROM configuration data

is loaded if EEPROM is detected. (EEPROM address 80H =

“00”).

Spread Spectrum Support

The FPD-Link receiver supports graphics controllers with

Spread Spectrum interfaces for reducing EMI. The Spread

Spectrum method supported is Center Spread. A maximum

of 2% Center Spread at a modulation frequency of 200 KHz

is supported.

8 to 6 Bit Translator

8-bit data is reduced to a 6-bit data path via a time multi-

plexed dithering technique or a simple truncation of the

LSBs. This function is enabled via the Input Control Register

bits 4 and 3. See

Table 2 Input Format Control register.

Data Alignment

This function delays and aligns data to match the CD/panel

architecture. Programmable selections in the Output Format

Control Register bits 0 and 1 provide support for various

LCD panel architectures. See

Figures 12, 13, 14, 15, 16 for

additional explanation.

Dual Bus, Single Port CD Interface

When interfacing two busses to a bank of single port column

drivers, the RGB data must be aligned/delayed with respect

to the size of the column drivers being used. The CD Size

of up to 384 outputs (128 pixels).

Dual Bus, Dual Port CD Interface

When interfacing with dual port column drivers, data is sim-

ply output with odd and even data on separate outputs.

Single Bus, Single Port CD Interface

The single bus, single port column driver interface provides

support of existing SVGA systems. All data is output on a

single bus. The second bus can be turned off when using

this configuration.

Output Formatting

The output formatting function provides several capabilities

to reduce noise EMI and to generate customized timing.

These capabilities are selectable/programmable via the Out-

put Format Control, Output Enable/Polarity Control, and Out-

put Drive Control Registers. See

Table 2 for specific bit

definitions.

Data Bus Skewing

This function aligns the two output channels in either a

non-skewed data format (simultaneous switching) or a

skewed data format. The skewed format delays the even

channel data and control by 1⁄2 clock. This reduces the

number of outputs which switch simultaneously. See Figures

12, 13, 14, 15, 16. Data Bus Skewing is enabled by setting

bit 2 in the Output Format Control register.

Programmable Slew Rates

Programmable edge rates allow the Data, Polarity, Start

Pulse, and Clock outputs to be adjusted for better imped-

ance matching for noise and EMI reduction. Bits [7:6] of the

Output Enable/Polarity Control Register control OSP and

ESP outputs. The Output Drive Control register control the

OCLK, ECLK, ORGB/OPOL, ERGB/EPOL outputs.

Polarity Generation

When enabled, a polarity indication (OPOL, EPOL) is output

for each data bus. When in the dual bus output configuration,

if the number of transitions from pixel to pixel exceed 18 bits

from a total of 36 bits, the data is then inverted and a polarity

indication corresponding to that bus is set active. In the

single bus (ORGB bus) applications such as SVGA, when

the number of pixel to pixel transitions exceed 9 bits from a

total of 18 bits, the data is inverted and the OPOL is set

active. This features requires the use of a CD with a polarity

input. In SKEWED dual output data bus applications, OPOL

and EPOL are aligned with their respective buses and

should be used as the Polarity generation input to the CD

which supports dual bus/Polarity generation. In Non-Skewed

dual output bus applications, OPOL is aligned with both data

buses and should be used as the Polarity Generation input

to the CD. The polarity function is enabled by setting bit 6 of

the Output Format Control register (EEPROM address D2).

The OCLK and ECLK polarity is also programmable. Inver-

sion and TRI-STATE control of OCLK and ECLK is provided

by bits [3:0] of the Output Enable/Polarity Control Register.

The ERGB/ESP/EPOL and ORGB/OSP/OPAL outputs can

be disabled (TRI-STATE) using bits [5:4] of the Output

Enable/Polarity Control register.

Programmable Positioning of CD Start Pulse

The position of the CD Start Pulse is programmable. This

allows use with column drivers having non-standard start

pulse timing. The CD Start Pulse position is determined by

bits [3:0] of the Output Format Control Register (EEPROM

address D3).

Data Blanking

Data, Polarity, Start Pulse and Clock can be blanked (forced

to “0”) during horizontal and/or vertical blanking periods.

GPO [8] is programmed to correspond to display periods.

When GPO [8] is low, outputs are forced to “0”. This reduces

amount of switching over the frame time thus reducing

power. See GPO programming procedure in

APPENDIX A:

GPO Programming Examples.

Line Inversion

When enabled (Bit 3 of the Output Format Register), the

polarity of the output data is determined by GPO [0]. Bit 4

defines the relationship between GPO [0] and the output

data. Bit 5 provides a variation of this where the Odd and

Even data is of different polarity. This could be used in a

system with CDs on both top and bottom of the panel in

which dot inversion is desired.

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