AD5601 datasheet(16/21 Pages) AD

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AD5601/AD5611/AD5621

Data Sheet

Rev. H | Page 16 of 21

POWER-ON RESET

The AD5601/AD5611/AD5621 contain a power-on reset circuit

that controls the output voltage during power-up. The DAC

there until a valid write sequence is made to the DAC. This is

useful in applications in which it is important to know the state

of the DAC output while it is in the process of powering up.

POWER-DOWN MODES

The AD5601/AD5611/AD5621 have four separate modes of

operation. These modes are software-programmable by setting

two bits (DB15 and DB14) in the control register. Table 6 shows

how the state of the bits corresponds to the operating mode of

the device.

Table 6. Operating Modes of the AD5601/AD5611/AD5621

DB15

DB14

Operating Mode

Normal operation

Power-down modes:

1 kΩ to GND

100 kΩ to GND

Three-state

When both bits are set to 0, the part has normal power

consumption of 100 µA maximum at 5 V. However, for the

three power-down modes, the supply current falls to typically

0.2 µA at 3 V.

Not only does the supply current fall, but the output stage is

also internally switched from the output of the amplifier to a

resistor network of known values. This has the advantage that

the output impedance of the part is known while the part is in

power-down mode.

There are three different options: the output is connected

internally to GND through a 1 kΩ resistor or a 100 kΩ resistor,

or the output is left open-circuited (three-stated). Figure 45

shows the output stage.

Figure 45. Output Stage During Power-Down

The bias generator, output amplifier, resistor string, and other

associated linear circuitry are all shut down when power-down

mode is activated. However, the contents of the DAC register

are unaffected when in power-down. The time to exit power-

down is typically 13 µs for VDD = 5 V and 16 µs for VDD = 3 V.

See Figure 21 for a plot.

MICROPROCESSOR INTERFACING

AD5601/AD5611/AD5621 to ADSP-2101 Interface

Figure 46 shows a serial interface between the AD5601/

AD5611/AD5621 and the ADSP-2101. The ADSP-2101 should

be set up to operate in SPORT transmit alternate framing mode.

The ADSP-2101 SPORT is programmed through the SPORT

control register and should be configured as follows: internal

clock operation, active low framing, and 16-bit word length.

Transmission is initiated by writing a word to the Tx register

after the SPORT is enabled.

Figure 46. AD5601/AD5611/AD5621 to ADSP-2101 Interface

AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

Figure 47 shows a serial interface between the AD5601/

AD5611/AD5621 and the 68HC11/68L11 microcontroller. SCK

of the 68HC11/68L11 drives the SCLK of the AD5601/AD5611/

AD5621, while the MOSI output drives the serial data line of

the DAC. The SYNC signal is derived from a port line (PC7).

The setup conditions for correct operation of this interface are

as follows: the 68HC11/68L11 should be configured so that the

CPOL bit is 0 and the CPHA bit is 1. When data is being trans-

mitted to the DAC, the SYNC line is taken low (PC7). When the

68HC11/68L11 are configured as indicated, data appearing on

the MOSI output is valid on the falling edge of SCK. Serial data

from the 68HC11/68L11 is transmitted in 8-bit bytes with only

eight falling clock edges occurring in the transmit cycle. Data is

transmitted MSB first. To load data to the AD5601/AD5611/

AD5621, PC7 is left low after the first eight bits are transferred

and a second serial write operation is performed to the DAC.

PC7 is taken high at the end of this procedure.

Figure 47. AD5601/AD5611/AD5621 to 68HC11/68L11 Interface

POWER-DOWN

CIRCUITRY

RESISTOR

NETWORK

VOUT

RESISTOR

STRING DAC

AMPLIFIER

AD5601/AD5611/

AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS

SCLK

SYNC

SDIN

SCLK

ADSP-2101*

68HC11/

68L11*

AD5601/AD5611/

AD5621*

*ADDITIONAL PINS OMITTED FOR CLARITY

PC7

SCK

MOSI

SYNC

SCLK

SDIN

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