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AD5025 датащи(PDF) 13 Page - Analog Devices |
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AD5025 датащи(HTML) 13 Page - Analog Devices |
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13 / 25 page ![]() Data Sheet AD5025/AD5045/AD5065 Rev. A | Page 13 of 25 24 20 14 8 4 01 5 7 10 CAPACITANCE (nF) 6 10 12 22 18 16 39 24 6 8 VDD = 5V, VREF = 3.0V TA = 25°C Figure 30. Settling Time vs. Capacitive Load CH1 5V CH2 2V M2µs A CH1 2.5V 2 1 T 11% VOUT CLR Figure 31. Hardware CLR 10 0 –10 –20 –60 10 100 1000 10000 FREQUENCY (kHz) –30 –40 –50 CH A CH B CH C CH D 3dB POINT Figure 32. Multiplying Bandwidth 0.0010 0.0008 0.0006 0.0004 0.0002 0 –0.0002 –0.0004 –0.0006 –0.0008 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 CURRENT (mA) CODE = MIDSCALE VDD = 5V, VREF = 4.096V VDD = 5.5V Figure 33. Typical Output Load Regulation 0.10 –0.10 –0.08 –0.06 –0.04 –0.02 0 0.02 0.04 0.06 0.08 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 IOUT (mA) CODE = MIDSCALE VDD = 5V, VREF = 4.096V Figure 34. Typical Current Limiting Plot CH1 50mV CH2 5V M4µs A CH2 1.2V T 8.6% CH1 295mV p-p VOUT SCLK Figure 35. Glitch Upon Entering Power-Down (1 kΩ to GND) from Zero Scale, No Load |
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