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2

Connection Diagram

Pin Description

Logic Symbol

IEEE/IEC

Truth Table

Note:

1. This configuration is nonstable; that is, it will not persist

when preset and clear inputs return to their inactive

(HIGH) state.

Pin Names

Description

Data Inputs

Clock Pulse Inputs

Direct Clear Inputs

Direct Preset Inputs

Output

Inputs

Outputs

Function

CLR

PR

DCK

Q

Q

LH

XX

LH

Clear

HL

XX

HL

Preset

LL

X

X

HH

L

L

H

HH

H

H

L

HH

X

No Change