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AD5696/AD5694

Data Sheet

Rev. B | Page 16 of 24

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5696/AD5694 are quad, 16-/12-bit, serial input, voltage

output DACs that operate from supply voltages of 2.7 V to 5.5 V.

Data is written to the AD5696/AD5694 in a 24-bit word format

via a 2-wire serial interface. The AD5696/AD5694 incorporate a

power-on reset circuit to ensure that the DAC output powers up

to a known output state. The devices also have a software power-

down mode that reduces the current consumption to 4 µA.

TRANSFER FUNCTION

Because the input coding to the DAC is straight binary, the ideal

output voltage is given by









REF

OUT

Gain

where:

VREF is the value of the external reference.

Gain is the gain of the output amplifier and is set to 1 by default.

The gain can be set to 1 or 2 using the gain select pin. When the

GAIN pin is tied to GND, all four DAC outputs have a span of

0 V to VREF. When this pin is tied to VDD, all four DAC outputs

have a span of 0 V to 2 × VREF.

D is the decimal equivalent of the binary code that is loaded to

the DAC register as follows: 0 to 4095 for the 12-bit AD5694,

and 0 to 65,535 for the 16-bit AD5696.

N is the DAC resolution (12 bits or 16 bits).

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an

output amplifier. Figure 33 shows a block diagram of the DAC

architecture.

Figure 33. Single DAC Channel Architecture Block Diagram

The resistor string structure is shown in Figure 34. Each resistor

in the string has a value R. The code loaded to the DAC register

determines the node on the string from which the voltage is

tapped off and fed into the output amplifier. The voltage is tapped

off by closing one of the switches that connect the string to the

amplifier. Because the AD5696/AD5694 are a string of resistors,

they are guaranteed monotonic.

Figure 34. Resistor String Structure

Output Amplifiers

The output buffer amplifier can generate rail-to-rail voltages on

its output for an output range of 0 V to VDD. The actual range

depends on the value of VREF, the GAIN pin, the offset error,

and the gain error. The GAIN pin selects the gain of the output.

•

When this pin is tied to GND, all four outputs have a gain

of 1, and the output range is from 0 V to VREF.

•

When this pin is tied to VDD, all four outputs have a gain

of 2, and the output range is from 0 V to 2 × VREF.

The output amplifiers are capable of driving a load of 1 kΩ in

parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼

to ¾ scale settling time of 5 µs.

INPUT

DAC

RESISTOR

STRING

REF (+)

VREF

GND

REF (–)

VOUTX

GAIN

(GAIN = 1 OR 2)

TO OUTPUT

AMPLIFIER

VREF

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