Data Sheet

AD5693R/AD5692R/AD5691R/AD5693

Rev. D | Page 9 of 26

3

GND

4

A0

1

2

LDAC

6 SDA

5 SCL

AD5693R/

AD5692R/

AD5691R/

AD5693

TOP VIEW

(Not to Scale)

NOTES

1. CONNECT THE EXPOSED PAD TO GND.

Figure 6. AD5693R/AD5692R/AD5691R/AD5693 Pin Configuration, 8-Lead LFCSP, LDAC Option

Table 8. AD5693R/AD5692R/AD5691R/AD5693 Pin Function Descriptions, 8-Lead LFCSP, LDAC Option

Pin No.

Mnemonic

Description

1

Power Supply Input. These devices can be operated from 2.7 V to 5.5 V. Decouple the supply to GND.

2

LDAC

Load DAC. Transfers the content of the input register to the DAC register. It can be operated in two modes,

asynchronously and synchronously, as shown in Figure 4. This pin can be tied permanently low and the DAC

updates when new data is written to the input register.

3

GND

Ground Reference.

4

A0

Programmable Address for Multiple Package Decoding. The address pin can be updated on-the-fly.

5

SCL

Serial Clock Line.

6

SDA

Serial Data Input/Output.

7

Reference Input/Output. In the AD5693R/AD5692R/AD5691R, this is a reference output pin by default. In the AD5693,

this pin is a reference input only. It is recommended to use a 10 nF decoupling capacitor for the internal reference.

8

Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.

EPAD

Exposed Pad. Connect the exposed pad to GND.