AD5758 datasheet(32/72 Pages) AD

32 / 72 page

AD5758

Data Sheet

Rev. 0 | Page 32 of 72

Transfer Function

Table 8 shows the input code to ideal output voltage relationship

for the AD5758 for straight binary data coding of the ±5 V

output range.

Table 8. Ideal Output Voltage to Input Code Relationship

Digital Input, Straight Binary

Data Coding

Analog Output

MSB

LSB

VOUT

1111

+2 VREF × (32,767/32,768)

1111

1110

+2 VREF × (32,766/32,768)

1000

0000

0 V

0000

0001

−2 VREF × (32,767/32,768)

0000

−2 VREF

POWER-ON STATE OF THE AD5758

On initial power-on or a device reset of the AD5758, the voltage

and current output channels are disabled. The VIOUT fault

protection switch is open, as is the switch connecting VIOUT via

a 30 kΩ pull-down resistor to AGND. Both of these switches can

be enabled via the DCDC_CONFIG1 register and the DCDC_

CONFIG2 register, respectively. VDPC+ is internally driven to

4.8 V on power-on, until the dc-to-dc converter is enabled.

After device power-on, or a device reset, a calibration memory

refresh command is required (see the Programming Sequence

to Enable the Output section). It is recommended to wait 500

μs minimum after writing this command, before writing further

instructions to the device to allow time for internal calibrations

to take place (see Figure 92).

Power-On Reset

3.3V

LDO

POWER-ON

RESET

SOFTWARE

RESET

HARDWARE

RESET

INT_AVCC

RESET

SDI

SCLK

VLDO

AVDD2

SYNC

Figure 76. Power-On Reset Block Diagram

The AD5758 incorporates a power-on reset circuit that ensures the

AD5758 is held in reset while the power supplies are at a level

insufficient to allow reliable operation. The power-on reset

circuit (see Figure 76) monitors the AVDD2 generated VLDO and

INT_AVCC voltages, the RESET pin, and the SPI reset signal.

The power-on reset circuit keeps the AD5758 in reset until the

voltages on the VLDO and INT_AVCC nodes are sufficient for

reliable operation. If the power-on circuit receives a signal from

the RESET pin, or if a software reset is written to the AD5758 via

the SPI interface, the AD5758 is reset. Do not write SPI commands

to the device within 100 μs of a reset event.

POWER SUPPLY CONSIDERATIONS

The AD5758 has four supply rails: AVDD1, AVDD2, AVSS, and

VLOGIC. See Table 1 for the voltage range of the four supply rails

and the associated conditions.

AVDD1 Considerations

AVDD1 is the supply rail for the dc-to-dc converter and can range

from 7 V to 33 V. Although the maximum value of AVDD1 is 33 V

and the minimum value of AVSS is −33 V, the maximum operating

range of |AVDD1 to AVSS| is 60 V. VDPC+ is derived from AVDD1, and its

value depends on the mode of operation of the dc-to-dc converter.

The dc-to-dc converter requires a sufficient level of margin to be

maintained between AVDD1 and VDPC+ to ensure the dc-to-dc

circuitry operates correctly. This margin is 5% of the maximum

VDPC+ voltage for a given mode of operation.

Table 9. AVDD1 to VDPC+ Margin

Mode of Operation

VDPC+ Maximum

DPC Voltage Mode

15 V

DPC Current Mode

(IOUT maximum × RLOAD) + IOUT headroom

PPC Current Mode

DCDC_CONFIG1[4:0] programmed value

See the Power Dissipation Control section for further details on

the dc-to-dc converter modes of operation.

Assuming DPC current mode,



IOUT maximum = 20 mA; RLOAD = 1 kΩ



IOUT headroom = 2.5 V



VDPC+ maximum = 20 V + 2.5 V = 22.5 V

|VDPC+ to AVDD1| headroom can be calculated as 5% of 22.5 V =

1.125 V. Therefore, AVDD1 (minimum) = 22.5 V + 1.125 V =

23.625 V. Assuming a worst case AVDD1 supply rail tolerance of

±10%, this example requires an AVDD1 supply rail of

approximately 26.25 V.

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