AD5697R

Data Sheet

Rev. B | Page 8 of 27

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 3. 16-Lead LFCSP Pin Configuration

Figure 4. 16-Lead TSSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

LFCSP

TSSOP

1

3

Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

16

2

NC

No Connect. Do not connect to this pin.

2

4

GND

Ground Reference Point for All Circuitry on the Part.

3

5

Power Supply Input. This part can be operated from 2.7 V to 5.5 V. Decouple the supply with a

10 μF capacitor in parallel with a 0.1 μF capacitor to GND.

4

6

NC

No Connect. Do not connect to this pin.

5

7

Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

6

8

SDA

Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the

24-bit input shift register. SDA is a bidirectional, open-drain data line that should be pulled to the

supply with an external pull-up resistor.

7

9

LDAC

LDAC can be operated in two modes, asynchronous and synchronous. Pulsing this pin low allows

either or both DAC registers to be updated if the input registers have new data. This allows both DAC

outputs to simultaneously update. This pin can also be tied permanently low.

8

10

GAIN

9

11

Digital Power Supply. Voltage ranges from 1.62 V to 5.5 V.

10

12

A0

Address Input. Sets the first LSB of the 7-bit slave address.

11

13

SCL

Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit

input register.

12

14

A1

Address Input. Sets the second LSB of the 7-bit slave address.

13

15

RESET

Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC

pulses are ignored. When RESET is activated, the input register and the DAC register are updated

with zero scale or midscale, depending on the state of the RSTSEL pin. If the pin is forced low at

power-up, the POR circuit does not initialize correctly until the pin is released.

14

16

RSTSEL

Power-On Reset Select. Tying this pin to GND powers up both DACs to zero scale. Tying this pin to

15

1

Reference Voltage. The AD5697R has a common reference pin. When using the internal reference,

this is the reference output pin. When using an external reference, this is the reference input pin.

The default for this pin is as a reference output.

17

Not applicable

EPAD

Exposed Pad. The exposed pad must be tied to GND.

12

11

10

1

3

4

A1

SCL

A0

2

GND

NC

TOP VIEW

(Not to Scale)

AD5697R

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

2. NC = NO CONNECT. DO NOT CONNECT TO

THIS PIN.

1

2

3

4

5

6

7

8

NC

GND

NC

SDA

16

15

14

13

12

11

10

9

RESET

A1

SCL

GAIN

LDAC

A0

RSTSEL

TOP VIEW

(Not to Scale)

AD5697R

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO

THIS PIN.